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Patent # Description
US-9,768,760 Synchronized semiconductor device with phase adjustment circuit
According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse...
US-9,768,378 Cross-point memory and methods for fabrication of same
The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,768,377 Magnetic cell structures, and methods of fabrication
A magnetic cell structure comprises a seed material including tantalum, platinum, and ruthenium. The seed material comprises a platinum portion overlying a...
US-9,768,376 Magnetic memory cells, semiconductor devices, and methods of operation
A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be...
US-9,768,366 Solid state optoelectronic device with preformed metal support substrate
A wafer-level process for manufacturing solid state lighting ("SSL") devices using large-diameter preformed metal substrates is disclosed. A light emitting...
US-9,768,330 Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in...
Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in...
US-9,768,271 Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method...
US-9,768,194 Methods of forming memory arrays
A method of forming a memory array includes filling a circular hole that is lined with a charge trapping layer with a conductor, forming a first slot and a...
US-9,768,181 Ferroelectric memory and methods of forming the same
Ferroelectric memory and methods of forming the same are provided. An example memory cell can include a buried recessed access device (BRAD) formed in a...
US-9,768,177 Method of forming conductive material of a buried transistor gate line and method of forming a buried...
A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a...
US-9,768,175 Semiconductor devices comprising gate structure sidewalls having different angles
The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first...
US-9,768,149 Semiconductor device assembly with heat transfer structure formed from semiconductor material
Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor...
US-9,768,147 Thermal pads between stacked semiconductor dies and associated systems and methods
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the...
US-9,768,134 Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects
A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in...
US-9,768,123 Semiconductor device structures including a distributed bragg reflector
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having...
US-9,768,121 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
US-9,768,021 Methods of forming semiconductor device structures including metal oxide structures
Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for...
US-9,767,962 Apparatuses, multi-chip modules and capacitive chips
Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and...
US-9,767,921 Timing based arbiter systems and circuits for ZQ calibration
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips....
US-9,767,919 Systems and methods for testing a semiconductor memory device having a reference memory array
Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first...
US-9,767,909 Memory cell programming utilizing conditional enabling of memory cells
Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of...
US-9,767,904 Memory with three transistor memory cell device
Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a...
US-9,767,898 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,767,896 Apparatuses and methods for accessing memory cells in semiconductor memories
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to...
US-9,767,894 Programming memories with stepped programming pulses
Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to...
US-9,767,886 Memory command received within two clock cycles
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,767,880 Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a...
US-9,767,865 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
US-9,767,864 Apparatuses and methods for storing a data value in a sensing circuitry element
The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a...
US-9,767,860 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
US-9,767,857 Apparatus and methods to perform read-while write (RWW) operations
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a...
US-9,767,721 Inspection apparatus and inspection method
An inspection apparatus and an inspection method capable of reducing the effect of noises are provided. An inspection apparatus according to the present...
US-9,767,012 Systems and methods for memory system management based on thermal information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
US-9,766,837 Stripe mapping in memory
Examples of the present disclosure provide apparatuses and methods related to redundant array of independent disks (RAID) stripe mapping in memory. An example...
US-9,766,831 Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and...
US-9,766,830 Power consumption control
The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information...
US-9,762,247 Apparatuses with an embedded combination logic circuit for high speed operations
Apparatuses for performing combination logic operations with an combination logic circuit are disclosed. According to one embodiment, the apparatus comprises a...
US-9,762,215 Apparatuses and methods for voltage buffering
An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer...
US-9,761,797 Methods of forming structures
Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along...
US-9,761,715 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,761,621 Color filter array, imagers and systems having same, and methods of fabrication and use thereof
A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter...
US-9,761,599 Integrated structures containing vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory...
US-9,761,590 Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
US-9,761,580 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor...
US-9,761,564 Layout of transmission vias for memory device
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory...
US-9,761,562 Semiconductor device packages including a controller element
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
US-9,761,559 Semiconductor package and fabrication method thereof
A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both...
US-9,761,540 Wafer level package and fabrication method thereof
A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is...
US-9,761,474 Methods for processing semiconductor devices
Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric...
US-9,761,457 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
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