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Patent # Description
US-1,038,9359 Buffer circuit
Apparatuses for providing buffer circuits a semiconductor device are described. An example apparatus includes a plurality of inverters and a transistor having...
US-1,038,9238 Charge pumps and methods of operating charge pumps
Methods of operating a charge pump, and charge pumps configured to perform similar methods, involve monitoring a level of a supply voltage of the charge pump,...
US-1,038,9027 Method and apparatus for sensing environmental parameters using wireless sensor(s)
A method includes varying, by a tuning module of a passive radio RFID sensor, a reactive component impedance coupled to the tuning module and an antenna of the...
US-1,038,8872 Memory cell materials and semiconductor device structures
A method of forming a memory cell material comprises forming a first portion of a dielectric material over a substrate by atomic layer deposition. Discrete...
US-1,038,8871 Memory cells and methods of forming memory cells
Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the...
US-1,038,8866 Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
US-1,038,8864 Transistors and methods of forming transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel...
US-1,038,8668 Integrated structures and methods of forming vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
US-1,038,8667 Memory cells, integrated structures and memory arrays
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a...
US-1,038,8665 Methods of forming an array of elevationally-extending strings of memory cells having a stack comprising...
An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative tiers and wordline tiers. The wordline tiers...
US-1,038,8658 Transistors, arrays of transistors, arrays of memory cells individually comprising a capacitor and an...
A transistor comprises semiconductor material that is generally L-shaped or generally mirror L-shaped in at least one straight-line vertical cross-section...
US-1,038,8657 Semiconductor device having a memory cell and method of forming the same
There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the...
US-1,038,8635 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-1,038,8630 Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a...
US-1,038,8606 Integrated assemblies having structures along a first pitch coupled with structures along a second pitch...
Some embodiments include a method of forming an integrated assembly. Conductive lines are formed to extend along a first direction, and are spaced from one...
US-1,038,8601 Semiconductor devices including conductive lines and methods of forming the semiconductor devices
A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion,...
US-1,038,8564 Method for fabricating a memory device having two contacts
A memory device with a dielectric layer or an air gap between contacts and a method of making the same are disclosed. The method comprises a series of steps...
US-1,038,8393 Apparatus and methods for debugging on a host and memory device
The present disclosure includes apparatus and methods for debugging on a host and memory device. An example apparatus comprises a memory device having an array...
US-1,038,8388 Responding to power loss
Apparatus, and methods of operating similar apparatus, might include an array of memory cells and a differential storage device configured to receive...
US-1,038,8384 Determining data states of memory cells
Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in...
US-1,038,8382 Methods and apparatus for programming memory
Methods of operating a memory include determining a target voltage level for an access line voltage, determining a target overdrive voltage level for gating the...
US-1,038,8379 Apparatuses and methods for automated dynamic word line start voltage
An apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open...
US-1,038,8373 Apparatuses and methods for sensing memory cells
Sensing memory cells can include: applying a voltage ramp to a group of memory cells to sense their respective states; sensing when a first switching event...
US-1,038,8363 Apparatuses and methods for detecting a row hammer attack with a bandpass filter
Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address,...
US-1,038,8362 Half-width, double pumped data path
Memory devices with half-width data path or data buses clocked by double-pumped strobe signals are disclosed herein. The methods and devices may employ a single...
US-1,038,8361 Differential amplifier schemes for sensing memory cells
Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a...
US-1,038,8360 Utilization of data stored in an edge section of an array
An example apparatus includes a memory device having first sensing circuitry positioned adjacent an edge of an edge array section and selectably coupled to a...
US-1,038,8354 Pre-writing memory cells of an array
Methods, systems, and devices for operating a memory cell or memory cells are described. Cells of a memory array may be pre-written, which may include writing...
US-1,038,8353 Canceling memory cell variations by isolating digit lines
A memory device may include a digit line, a ferroelectric memory cell coupled with the digit line, a first capacitor including a first node and a second node,...
US-1,038,8352 Parallel access techniques within memory sections through section independence
A memory device having a plurality sections of memory cells, such as ferroelectric memory cells may provide for concurrent access to memory cells within...
US-1,038,8351 Wear leveling for random access and ferroelectric memory
Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g.,...
US-1,038,8341 Semiconductor device including a clock adjustment circuit
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in...
US-1,038,8340 Apparatuses, circuits, and methods for biasing signal lines
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled...
US-1,038,8335 Sense amplifier schemes for accessing memory cells
A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation...
US-1,038,8334 Scan chain operation in sensing circuitry
An apparatus can include an array of memory cells coupled to sensing circuitry. The sensing circuitry can include a sense amplifier and a compute component. The...
US-1,038,8333 Apparatuses and methods to selectively perform logical operations
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry...
US-1,038,8330 Using out-of-band signaling to communicate with daisy chained nonvolatile memories
Memory devices connected in a chain topology to a host controller that communicate using Low Voltage Differential Signaling (LVDS) and out-of-band signaling.
US-1,038,7341 Apparatuses and methods for asymmetric input/output interface for a memory
Apparatuses and methods for asymmetric input output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The...
US-1,038,7338 Memory tile access and selection patterns
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile...
US-1,038,7336 Memory protection based on system state
Disclosed in some examples are memory systems, computing systems, and machine readable mediums for protecting memory at identified addresses based upon access...
US-1,038,7299 Apparatuses and methods for transferring data
The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises a cache coupled to an array of memory cells and...
US-1,038,7281 Flash memory block retirement policy
Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service...
US-1,038,7121 Apparatuses and methods for random number generation
The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device...
US-1,038,7060 Memory device configuration commands
Apparatuses and methods for configuring a memory device using configuration commands are provided. A method can include executing a first command while the...
US-1,038,7058 Apparatuses and methods to change data category values
The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality...
US-1,038,7056 Obfuscation-enhanced memory encryption
The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation,...
US-1,038,7055 Multiple endianness compatibility
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of...
US-1,038,7048 Memory devices configured to latch data for output in response to an edge of a clock signal generated in...
Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock...
US-1,038,7046 Bank to bank data transfer
The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells...
US-1,038,7039 Data storage management
A method of managing a plurality of storage devices. The method comprises at a first device connected to the plurality of storage devices via a switch,...
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