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Patent # Description
US-9,793,884 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-9,793,282 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,793,124 Semiconductor structures
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate...
US-9,793,008 Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
US-9,792,973 Ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground...
US-9,792,964 Apparatus of offset voltage adjustment in input buffer
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a...
US-9,792,960 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-9,792,958 Active boundary quilt architecture memory
Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may...
US-9,792,097 Method and apparatus for compiling regular expressions
Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between...
US-9,791,629 Active alignment of optical fiber to chip using liquid crystals
Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical...
US-9,786,841 Semiconductor devices with magnetic regions and attracter material and methods of fabrication
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
US-9,786,719 Method for base contact layout, such as for memory
Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
US-9,786,684 Apparatuses having a ferroelectric field-effect transistor memory array and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates...
US-9,786,643 Semiconductor devices comprising protected side surfaces and related methods
Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A...
US-9,786,612 Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
US-9,786,586 Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
US-9,786,548 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-9,786,544 Floating body memory cell apparatus and methods
Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically...
US-9,786,514 Semiconductor package with sidewall-protected RDL interposer
A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall...
US-9,786,504 Method for forming a patterned layer
A method for forming a patterned layer is provided. The method comprises forming a first material layer over a first substrate, forming a photoresist layer on...
US-9,786,475 Systems and methods for plasma processing of microfeature workpieces
Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber...
US-9,786,366 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address...
US-9,786,352 Semiconductor memory device including refresh operations having first and second cycles
Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells,...
US-9,786,349 Cell performance recovery using cycling techniques
Methods, systems, and devices for memory array operation are described. A series of pulses may be applied to a fatigued memory cell to improve performance of...
US-9,786,348 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-9,786,347 Cell-specific reference generation and sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for...
US-9,786,346 Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
Virtual ground sensing circuits, electrical systems, computing devices, and related methods are disclosed. A virtual ground sensing circuit includes a sense...
US-9,786,345 Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of...
US-9,786,335 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,786,334 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,786,332 Semiconductor device package with mirror mode
Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor...
US-9,785,847 Analyzing data using a hierarchical structure
Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can...
US-9,785,603 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,785,588 Methods and systems for devices with self-selecting bus decoder
Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a...
US-9,785,171 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
US-9,784,788 Fault isolation system and method for detecting faults in a circuit
The present invention provides a method and a fault isolation system for detecting errors in an integrated circuit. One feature of the present invention is...
US-9,781,365 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-9,780,786 Apparatus and method for standby current control of signal path
Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second...
US-9,780,654 Analog assisted digital switch regulator
A device includes a digital switch regulator to supply an output voltage and a first current to a load based on a reference voltage. The device also includes an...
US-9,780,184 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-9,780,115 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,780,110 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
US-9,780,107 Methods of forming integrated circuit devices
Methods of forming integrated circuit devices containing memory cells over a first region of a semiconductor substrate and gate structures over a second region...
US-9,780,103 Methods of forming integrated structures
Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has...
US-9,780,102 Memory cell pillar including source junction plug
Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the...
US-9,780,079 Semiconductor die assembly and methods of forming thermal paths
Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally...
US-9,780,052 Collars for under-bump metal structures and associated systems and methods
The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and...
US-9,780,029 Semiconductor constructions having conductive lines which merge with one another
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
US-9,779,839 Methods for providing redundancy in a memory array comprising mapping portions of data associated with a...
Methods for providing redundancy in a memory include mapping a portion of first data associated with an address of the memory determined to indicate a defective...
US-9,779,829 Erasing memory segments in a memory block of memory cells using select gate control line voltages
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
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