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Patent # Description
US-1,026,3183 Methods of forming an array of cross point memory cells
A method of forming an array of cross point memory cells comprises forming spaced conductive lower electrode pillars for individual of the memory cells being...
US-1,026,3039 Memory cells having resistors and formation of the same
The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line,...
US-1,026,2961 Semiconductor devices having discretely located passivation material, and associated systems and methods
Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond...
US-1,026,2922 Semiconductor device having through-silicon-via and methods of forming the same
Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a...
US-1,026,2745 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory...
US-1,026,2739 Devices including memory arrays, row decoder circuitries and column decoder circuitries
Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data...
US-1,026,2736 Multifunctional memory cells
The present disclosure includes multifunctional memory cells. A number of embodiments include a charge transport element having an oxygen-rich silicon...
US-1,026,2734 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-1,026,2721 Apparatuses and methods for cache invalidate
The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel...
US-1,026,2715 Multiple plate line architecture for multideck memory array
Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more...
US-1,026,2704 Apparatuses and methods for providing multiphase clock signals
Apparatuses and methods for providing multiphase clock signals are described. An example apparatus includes first, second, third and fourth clocked inverters,...
US-1,026,2701 Data transfer between subarrays in memory
The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells...
US-1,026,1914 Methods of memory address verification and memory devices employing the same
A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, and a controller configured to receive a...
US-1,026,1876 Memory management
The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of...
US-1,026,1713 Configurable operating mode memory device and methods of operation
Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for...
US-1,026,1691 Computing reduction and prefix sum operations in memory
The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing...
US-1,026,1123 Semiconductor device structures for burn-in testing and methods thereof
A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly...
US-1,025,7944 Board edge connector
Apparatuses and methods for forming serial advanced technology attachment (SATA) board edge connectors with electroplated hard gold contacts. One example method...
US-1,025,6998 Reducing supply noise in current mode logic transmitters
Methods, systems, and devices for mitigating supply noise in single-ended current mode logic (CML) transmitters are described. A first current source may...
US-1,025,6817 Methods and systems for averaging impedance calibration
A semiconductor device also includes programmable termination components and a calibration circuit. The calibration circuit generates impedance calibration...
US-1,025,6795 Pipelined latches to prevent metastability
Memory devices may receive data from data processing devices for storage and processing during write operations. The received data may be accompanied by a data...
US-1,025,6406 Semiconductor structures including liners and related methods
A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a...
US-1,025,6369 Solid state lighting devices with accessible electrodes and methods of manufacturing
Various embodiments of light emitting dies and solid state lighting ("SSL") devices with light emitting dies, assemblies, and methods of manufacturing are...
US-1,025,6367 Ultrathin solid state dies and methods of manufacturing the same
Various embodiments of SST dies and solid state lighting ("SSL") devices with SST dies, assemblies, and methods of manufacturing are described herein. In one...
US-1,025,6309 Memory cells having electrically conductive nanodots
Memory cells having electrically conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and...
US-1,025,6275 Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers and a plurality of...
US-1,025,6249 Integrated structures
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and ...
US-1,025,6216 Interconnect structures with intermetallic palladium joints and associated systems and methods
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
US-1,025,6214 Computer modules with small thicknesses and associated methods of manufacturing
Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module...
US-1,025,6098 Integrated assemblies containing germanium
Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface...
US-1,025,5975 Apparatuses and methods of reading memory cells
A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (.sub.VTH) region between a first state...
US-1,025,5967 Power reduction technique during write bursts
A memory device may include voltage regulation circuitry configured to supply a voltage signal between a high signal and a low signal. The memory device may...
US-1,025,5963 Apparatus having dice to perform refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first...
US-1,025,5193 Virtual address table
The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises:...
US-1,025,4995 UFS based idle time garbage collection management
Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data...
US-1,025,4976 Methods and systems for using state vector data in a state machine engine
A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore...
US-1,025,4782 Apparatuses for reducing clock path power consumption in low power dynamic random access memory
Apparatus and methods of reducing clock path power consumption are described herein. According to one embodiment, an example apparatus includes a clock control...
US-1,025,1233 Solid state lighting systems and associated methods of operation and manufacture
A lighting system includes a solid state lighting device capable of generating mixed light and a controller. The solid state lighting device includes light...
US-1,025,0139 Apparatuses and methods for a load current control circuit for a source follower voltage regulator
According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage,...
US-1,024,9819 Methods of forming semiconductor structures including multi-portion liners
A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a...
US-1,024,9806 Solid state optoelectronic device with preformed metal support substrate
A wafer-level process for manufacturing solid state lighting ("SSL") devices using large-diameter preformed metal substrates is disclosed. A light emitting...
US-1,024,9365 Two-part programming methods
Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be...
US-1,024,9358 Apparatuses and methods for configurable command and data input circuits for semiconductor memories
Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal...
US-1,024,9355 Apparatuses and methods for providing active and inactive clock signals to a command path circuit
Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active...
US-1,024,9354 Apparatuses and methods for duty cycle distortion correction of clocks
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive...
US-1,024,9350 Apparatuses and methods for parity determination using sensing circuitry
The present disclosure includes apparatuses and methods related to parity determinations using sensing circuitry. An example method can include protecting,...
US-1,024,9348 Apparatuses and methods for generating a voltage in a memory
Apparatuses and methods for generating a voltage are described. An example apparatus includes first, second, and third bias circuits configured to provide...
US-1,024,9345 Memories having select devices between access lines and in memory cells
Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each...
US-1,024,9187 Control server and control system for controlling traffic signals based on information from pressure sensors...
Provided are a control server and a control system both capable of preventing traffic accidents more effectively. The control server is configured to control...
US-1,024,8594 Programming interruption management
The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming...
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