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Patent # Description
US-1,012,8916 Wireless communication link using near field coupling
A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field...
US-1,012,8847 Apparatuses and methods for level shifting
Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first...
US-1,012,8843 Apparatuses and methods for partial bit de-emphasis
Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes...
US-1,012,8842 Output impedance calibration for signaling
Methods, systems, and devices for output impedance calibration for signaling are described. Techniques are provided herein to adjust impedance levels associated...
US-1,012,8802 Semiconductor device including amplifier
Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge...
US-1,012,8437 Semiconductor structures including memory materials substantially encapsulated with dielectric materials, and...
A semiconductor structure includes stack structures. Each of the stack structures comprises a first conductive material, a chalcogenide material over the first...
US-1,012,8315 Methods of forming phase change memory apparatuses
Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the...
US-1,012,8265 Memory cells, integrated structures and memory arrays
Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a...
US-1,012,8229 Semiconductor devices with package-level configurability
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first...
US-1,012,8217 Memory devices with controllers under memory packages and associated systems and methods
Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a...
US-1,012,8212 Semiconductor package and fabrication method thereof
A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be...
US-1,012,8183 Structure of integrated circuitry and a method of forming a conductive via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically...
US-1,012,8142 Semiconductor structures including carrier wafers and attached device wafers, and methods of forming such...
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars...
US-1,012,7994 Systems and methods for threshold voltage modification and detection
A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one...
US-1,012,7988 Temperature compensation in memory sensing
Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time...
US-1,012,7972 Apparatuses and methods including two transistor-one capacitor memory and for accessing same
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor...
US-1,012,7971 Systems and methods for memory cell array initialization
Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset...
US-1,012,7969 Memory device command receiving and decoding methods
Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding...
US-1,012,7965 Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage...
US-1,012,7963 Charge sharing between memory cell plates using a conductive path
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to...
US-1,012,7962 Unidirectional spin torque transfer magnetic memory cell structure
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices...
US-1,012,7954 Quantizing circuits having improved sensing
A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and...
US-1,012,6967 Sense operation flags in a memory device
In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell...
US-1,012,6947 Interconnect systems and methods using hybrid memory cube links to send packetized data over different...
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ...
US-1,012,6357 Methods of testing semiconductor devices comprising a die stack having protruding conductive elements
Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged...
US-1,012,2952 Anti-eclipse circuitry with tracking of floating diffusion reset level
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to...
US-1,012,1966 Semiconductor device structures including silicon-containing dielectric materials
A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals...
US-1,012,1906 Vertical memory strings, and vertically-stacked structures
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels...
US-1,012,1849 Methods of fabricating a semiconductor structure
A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a...
US-1,012,1824 Magnetic structures, semiconductor structures, and semiconductor devices
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The...
US-1,012,1799 Elevationally-extending strings of memory cells individually comprising a programmable charge storage...
A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the...
US-1,012,1766 Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive...
US-1,012,1745 Integrated circuit structures comprising conductive vias and methods of forming conductive vias
A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first...
US-1,012,1739 Multi-die inductors with coupled through-substrate via cores
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially...
US-1,012,1738 Semiconductor constructions
Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor...
US-1,012,1734 Semiconductor device
A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The...
US-1,012,1697 Semiconductor constructions; and methods for providing electrically conductive material within openings
Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a...
US-1,012,1670 Methods of fabricating semiconductor structures
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate...
US-1,012,1662 Methods of forming structures and methods of decreasing defect density
A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is...
US-1,012,1551 Detecting power loss in NAND memory devices
Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first...
US-1,012,1544 Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells
Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to...
US-1,012,1539 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program...
US-1,012,1526 Redundancy array column decoder for memory
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other...
US-1,012,1523 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-1,012,1521 Read threshold voltage selection
Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a...
US-1,012,0754 Data storage error protection
Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory...
US-1,012,0753 Methods and apparatuses for error correction
Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may...
US-1,012,0740 Apparatus and methods for debugging on a memory device
The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory...
US-1,012,0604 Data programming
Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a...
US-1,012,0404 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
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