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Patent # Description
US-9,818,756 Methods of forming a charge-retaining transistor having selectively-formed islands of charge-trapping material...
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes...
US-9,818,728 Interconnect structure with redundant electrical connectors and associated systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,625 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,622 Uniform back side exposure of through-silicon vias
Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate...
US-9,818,462 Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application....
US-9,818,459 Invert operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,817,678 Methods and systems for detection in a state machine
A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a...
US-9,817,392 Photolithography systems and associated methods of overlay error correction
Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for...
US-9,813,067 Clock signal and supply voltage variation tracking
Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a...
US-9,812,606 Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and...
Semiconductor device assemblies having solid-state transducer (SST) devices and associated semiconductor devices, systems, and are disclosed herein. In one...
US-9,812,455 Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
US-9,812,415 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
US-9,811,651 System and method for controlling user access to an electronic device
A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and...
US-9,811,258 Methods for controlling host memory access with memory devices and systems
The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment...
US-9,806,129 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,805,828 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-9,805,817 Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US-9,805,801 Memory devices and methods of their operation during a programming operation
Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected...
US-9,805,792 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-9,805,789 Oxide based memory
Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory...
US-9,805,786 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-9,805,783 Semiconductor device
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a...
US-9,805,772 Apparatuses and methods to selectively perform logical operations
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry...
US-9,804,350 Method of forming a hermetically sealed fiber to chip connections
Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated...
US-9,799,927 Repair apparatus of sheet type cell
A repair apparatus of a sheet type cell is capable of appropriately repairing and detoxifying defects of a sheet type cell having semiconductor characteristics....
US-9,799,727 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
US-9,799,707 Memory structures and arrays
Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes,...
US-9,799,658 Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support...
US-9,799,611 Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
US-9,799,562 Vias and conductive routing layers in semiconductor substrates
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method...
US-9,799,398 Memory cell verification circuits, memory cell sense circuits and memory cell verification methods
Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a...
US-9,799,388 Charge sharing between memory cell plates using a conductive path
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to...
US-9,799,378 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
US-9,798,601 Connection method
A failure of communication between a first device and a second device is managed. A failure of communication between the first device and the second device is...
US-9,793,884 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-9,793,282 Floating gate memory cells in vertical memory
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
US-9,793,124 Semiconductor structures
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate...
US-9,793,008 Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
US-9,792,973 Ferroelectric memory cell sensing
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may maintain a digit line voltage at a ground...
US-9,792,964 Apparatus of offset voltage adjustment in input buffer
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a...
US-9,792,960 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-9,792,958 Active boundary quilt architecture memory
Methods, systems, and apparatus that increase available memory or storage using active boundary areas in quilt architecture are described. A memory array may...
US-9,792,097 Method and apparatus for compiling regular expressions
Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between...
US-9,791,629 Active alignment of optical fiber to chip using liquid crystals
Devices and systems to perform optical alignment by using one or more liquid crystal layers to actively steer a light beam from an optical fiber to an optical...
US-9,786,841 Semiconductor devices with magnetic regions and attracter material and methods of fabrication
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
US-9,786,719 Method for base contact layout, such as for memory
Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
US-9,786,684 Apparatuses having a ferroelectric field-effect transistor memory array and related method
An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates...
US-9,786,643 Semiconductor devices comprising protected side surfaces and related methods
Methods of protecting semiconductor devices may involve forming trenches in streets between stacks of semiconductor dice on regions of a semiconductor wafer. A...
US-9,786,612 Methods of processing wafer-level assemblies to reduce warpage, and related assemblies
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...
US-9,786,586 Semiconductor package and fabrication method thereof
A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A...
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