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Wireless communication system with enhanced power management
A method is provided for a wireless communication device containing at least a main processor for data processing, and a transmitter and a receiver for wireless...
Reference voltage circuits and on-die termination circuits, methods for
updating the same, and methods for...
Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has...
Memory cells, methods of fabrication, and semiconductor devices
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
Ohmic contacts for semiconductor structures
A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl.sub.xN.sub.y material at...
Semiconductor-metal-on-insulator structures, methods of forming such
structures, and semiconductor devices...
Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first...
Devices and methods including an etch stop protection material
Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric...
Disabling electrical connections using pass-through 3D interconnects and
associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
Apparatuses and methods for charging a global access line prior to
accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
Threshold voltage distribution determination
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
Apparatuses for resetting an address counter during refresh operations
An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality...
Systems, circuits, and methods for charge sharing
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
Providing power availability information to memory
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
Chained bus method
Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single...
Direct communication with a processor internal to a memory device
Devices, systems, and methods of communicating information directly to a sequencer or a buffer in a memory device are provided. In some embodiments,...
A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through...
Phase interpolators and push-pull buffers
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase...
Vertical solid-state transducers having backside terminals and associated
systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
Solid state lighting devices without converter materials and associated
methods of manufacturing
Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a...
Semiconductor device including plural semiconductor chips stacked on
A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common...
Method of forming a semiconductor device comprising first and second
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
Semiconductor die assembly
A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to...
Apparatuses and methods for controlling wordlines and sense amplifiers
Apparatuses and methods for controlling word lines and sense amplifiers in a semiconductor device are described. An example apparatus includes: a sub word line...
Frequency synthesis for memory input-output operations
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components...
Apparatuses and methods for adjusting a delay of a command signal path
Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a command input buffer that receives...
Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
Data shift by elements of a vector in memory
Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift...
Concurrent memory operations
Subject matter disclosed herein relates to performing concurrent memory operations.
Systems and methods for reordering packet transmissions in a scalable
memory system protocol
A memory device includes a plurality of memory components that stores data and a processor communicatively coupled to the plurality of memory components. The...
An inspection apparatus capable of reducing the effect of noises is provided. An inspection apparatus according to the present invention includes a work table...
Memory elements using self-aligned phase change material layers and
methods of manufacturing same
A memory element and method of forming the same. The memory element includes a first electrode within a via in a first dielectric material. An insulating...
Three dimensional memory array architecture
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality...
STT-MRAM cell structures
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free...
Memory array having connections going through control gates
Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus...
Proximity coupling of interconnect packaging systems and methods
Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed...
Methods and systems for releasably attaching support members to
Methods and apparatuses for releasably attaching support members to microfeature workpieces to support members are disclosed herein. In one embodiment, for...
High aspect ratio openings
A capacitor forming method includes forming an electrically conductive support material over a substrate, with the support material containing at least 25 at %...
Apparatuses and methods for reducing read disturb
Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate...
Apparatus and methods of operating memory for exact and inexact searching
of feature vectors
Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the...
Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write...
Configuring and reconfiguring blocks of memory cells to store user data
and ECC data
A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a...
Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate...
Compositions for removing residues and related methods
Compositions for removing residues from a semiconductor structure. The compositions comprise water, a base, a polydentate chelator, a degasser, and a fluorine...
Semiconductor device having duty correction circuit
Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a...
Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising...
Self-aligned cross-point phase change memory-switch array
Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of...
Memory devices with stairs in a staircase coupled to tiers of memory cells
and to pass transistors directly...
In an example, a memory device includes a staircase comprising a flight of stairs and a plurality of pass transistors directly under the staircase. The stairs...
Array of conductive vias, methods of forming a memory array, and methods
of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
Methods of processing wafer-level assemblies to reduce warpage, and
Wafer-level methods of processing semiconductor devices may involve forming grooves partially through a molding material, the molding material located in...