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Patent # Description
US-1,018,1486 Elevated pocket pixels, imaging devices and systems including the same and method of forming the same
An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,...
US-1,018,1351 Increased NAND performance under high thermal conditions
Devices and techniques for increased NAND performance under high thermal conditions are disclosed herein. An indicator of a high-temperature thermal condition...
US-1,018,1344 Memory device write circuitry
Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main...
US-1,018,1343 Semiconductor device including a clock adjustment circuit
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in...
US-1,018,1341 Memory device including current generator plate
Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second...
US-1,018,0922 Methods and systems for devices with self-selecting bus decoder
Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a...
US-1,018,0920 Apparatuses and methods for asymmetric input/output interface for a memory
Apparatuses and methods for asymmetric input/output interfaces for memory are disclosed. An example apparatus may include a receiver and a transmitter. The...
US-1,018,0804 Obfuscation-enhanced memory encryption
The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation,...
US-1,017,8910 Drawer apparatus
A drawer apparatus capable of locking and unlocking a drawer without position control and motor stop control is provided. A lock frame is released from the hook...
US-1,017,7793 Error correction code (ECC) operations in memory
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a...
US-1,017,7198 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line...
US-1,017,7159 Memory cells and memory arrays
Some embodiments include memory cells having four transistors supported by a base, and vertically offset from the base. The four transistors are incorporated...
US-1,017,7152 Integrated assemblies comprising stud-type capacitors
Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a...
US-1,017,7122 High voltage solid-state transducers and solid-state transducer arrays having electrical cross-connections and...
Solid-state transducer ("SST") dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a...
US-1,017,7120 Stacked semiconductor dies including inductors and associated methods
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and...
US-1,017,6870 Multifunctional memory cells
The present disclosure includes multifunctional memory cells. A number of embodiments include a gate element, a charge transport element, a first charge storage...
US-1,017,6868 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually...
US-1,017,6862 Data strobe gating
Methods and devices for gating an internal data strobe from an input buffer of a memory device. The gating function occurs after a write operation ceases but...
US-1,017,6860 Refresh in non-volatile memory
The present disclosure includes apparatuses and methods related to refresh in memory. An example apparatus can refresh a memory cell of an array of memory cells...
US-1,017,6858 Adjusting instruction delays to the latch path in DDR5 DRAM
Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a...
US-1,017,6851 Loop structure for operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-1,017,6328 Self-measuring nonvolatile memory device systems and methods
One embodiment describes a computing system that includes a boot device. The boot device includes nonvolatile memory that stores startup routine instructions...
US-1,017,6091 Methods of operating a memory system including data collection and compression
Methods of operating a storage device include reading first data from a first storage location of a first memory of the storage device, storing the first data...
US-1,017,6040 Error correction code (ECC) operations in memory
The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to...
US-1,017,6039 Self-accumulating exclusive OR program
Methods and apparatus for Exclusive OR (XOR) programming of a memory device include a program internal to a device calculates parity or other values using an...
US-1,017,5915 Data randomization for flash memory
Data words written to an SSD device, or other device or output data stream, may be randomized using a seed based on physical addressing information, such as a...
US-1,017,5908 Systems and methods for providing file information in a memory system protocol
A controller of a memory device controls placement of data blocks by receiving, from a host electronic device, one or more commands of a memory system protocol....
US-1,017,5902 Managing host communication with a regulator in a low power mode
A solid-state drive (SSD) includes a connector communicatively coupling the SSD to a host device, a controller coupled to the connector, and a memory device....
US-1,017,1032 Apparatuses and methods for temperature independent oscillators
Apparatuses and methods for temperature independent oscillator circuits are disclosed herein. An example apparatus may include a pulse generator circuit...
US-1,017,0668 Solid state lighting devices with improved current spreading and light extraction and associated methods
Solid state lighting ("SSL") devices with improved current spreading and light extraction and associated methods are disclosed herein. In one embodiment, an SSL...
US-1,017,0639 3D memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional...
US-1,017,0545 Memory arrays
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom...
US-1,017,0493 Assemblies having vertically-stacked conductive structures
Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of...
US-1,017,0491 Memory including blocking dielectric in etch stop tier
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to...
US-1,017,0490 Memory device including pass transistors in memory tiers
Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through...
US-1,017,0448 Apparatus and method of power transmission sensing for stacked devices
Apparatuses for supplying power supply voltage in a plurality of dies are described. An example apparatus includes: a circuit board; a regulator on the circuit...
US-1,017,0389 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-1,017,0248 Structure and methods of forming the structure
Capacitors, apparatus including a capacitor, and methods for forming a capacitor are provided. One such capacitor may include a first conductor a second...
US-1,017,0196 Apparatuses and methods to control body potential in 3D non-volatile memory operations
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line...
US-1,017,0194 Asymmetrical multi-gate string driver for memory device
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials...
US-1,017,0193 Apparatus and methods of operating memory for negative gate to body conditions
Methods of operating a memory, and apparatus so configured, include applying a first voltage level to a first voltage node connected to a first end of a string...
US-1,017,0191 Electronic memory device having two portions that can be decoupled
A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory...
US-1,017,0189 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-1,017,0188 3D memory device including shared select gate connections between memory blocks
Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string...
US-1,017,0187 Apparatuses and methods using negative voltages in part of memory write read, and erase operations
Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The...
US-1,017,0183 Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells...
Some embodiments include methods of storing and retrieving data for an RRAM array. The array is subdivided into a plurality of memory bits, with each memory bit...
US-1,017,0174 Apparatus and methods for refreshing memory
Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes: a latch...
US-1,017,0173 Charge mirror-based sensing for ferroelectric memory
Methods, systems, and devices for a sensing scheme that extracts the full or nearly full remnant polarization charge difference between two logic states of a...
US-1,017,0169 Apparatuses and methods involving accessing distributed sub-blocks of memory cells
Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in...
US-1,017,0167 Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
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