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Patent # Description
US-9,633,988 Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus...
US-9,633,748 Multi-channel testing
Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a...
US-9,627,251 Forming array contacts in semiconductor memories
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
US-9,627,067 Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of...
US-9,627,052 Apparatuses and methods for current limitation in threshold switching memories
Apparatuses and methods are described herein for limiting current in threshold switching memories. In an example, an apparatus may include a plurality of first...
US-9,621,032 Generation of voltages
Voltage generation circuits are useful in the generation of internal voltages for use in integrated circuits. Voltage generation circuits may include a stage...
US-9,620,675 Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing
Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate...
US-9,614,516 Devices for shielding a signal line over an active region
A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region....
US-9,614,497 Semiconductor device and method for adjusting impedance of output circuit
An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode...
US-9,614,153 Methods of selectively doping chalcogenide materials and methods of forming semiconductor devices
Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating...
US-9,614,151 Method and apparatus providing multi-planed array memory device
A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions....
US-9,614,007 Memory arrays
Some embodiments include a memory array having a first memory cell adjacent to a second memory cell along a lateral direction. The second memory cell is...
US-9,614,006 Semiconductor constructions, and methods of forming cross-point memory arrays
Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one...
US-9,614,005 Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
US-9,614,004 Diode/superionic conductor/polymer memory structure
A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second...
US-9,613,978 Methods of forming semiconductor constructions
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically...
US-9,613,973 Memory having a continuous channel
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack...
US-9,613,943 Semiconductor device having output buffers and voltage path coupled to output buffers
An apparatus includes first and second data pads arranged adjacently to each other in a first direction without an intervention of a pad therebetween, first and...
US-9,613,902 Connections for memory electrode lines
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line...
US-9,613,864 Low capacitance interconnect structures and associated systems and methods
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
US-9,613,706 Programming and/or erasing a memory device in response to its program and/or erase history
A method includes sending a number of program/erase cycles from a memory of control logic of a memory device to a counter of the control logic, where the number...
US-9,613,695 Methods, devices and systems using over-reset state in a memory cell
Memory cells, devices and methods are disclosed, including those that involve applying a waveform to a resistive memory cell to program the memory cell to an...
US-9,613,676 Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a...
US-9,613,214 Self-measuring nonvolatile memory devices with remediation capabilities and associated systems and methods
Several embodiments of systems incorporating nonvolatile memory devices are disclosed herein. In one embodiment, a system can include a central processor (CPU)...
US-9,612,972 Apparatuses and methods for pre-fetching and write-back for a segmented cache memory
Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested...
US-9,612,954 Recovery for non-volatile memory after power loss
Non-volatile memory array can be recovered after a power loss. In one example, pages of a memory array are scanned to find a first free page after the power...
US-9,612,903 Updating reliability data with a variable node and check nodes
The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node,...
US-9,612,775 Solid state drive controller
A memory device may comprise circuitry to adjust between latency and throughput in transferring information through a memory port, wherein the circuitry may be...
US-9,612,750 Autonomous memory subsystem architecture
An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem...
US-9,612,605 Voltage regulator with current feedback
Generally discussed herein are apparatuses and methods for a voltage regulator with a current feedback loop. One such apparatus may include an amplifier, a...
US-9,612,413 Method and apparatus providing a coupled photonic structure
Described embodiments include optical connections for electronic-photonic devices, such as optical waveguides and photonic detectors for receiving optical waves...
US-9,610,593 Device for positioning nanoparticles
The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment,...
US-9,609,600 Wireless communication system with enhanced power management
A method is provided for a wireless communication device containing at least a main processor for data processing, and a transmitter and a receiver for wireless...
US-9,608,630 Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for...
Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has...
US-9,608,197 Memory cells, methods of fabrication, and semiconductor devices
A magnetic cell includes an attracter material proximate to a magnetic region (e.g., a free region). The attracter material is formulated to have a higher...
US-9,608,185 Ohmic contacts for semiconductor structures
A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl.sub.xN.sub.y material at...
US-9,608,119 Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices...
Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first...
US-9,608,000 Devices and methods including an etch stop protection material
Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric...
US-9,607,930 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
US-9,607,705 Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
US-9,607,692 Threshold voltage distribution determination
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
US-9,607,691 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-9,607,677 Apparatuses for resetting an address counter during refresh operations
An example apparatus includes an address counter configured to provide refresh addresses to a refresh circuit, wherein the address counter includes a plurality...
US-9,607,668 Systems, circuits, and methods for charge sharing
Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage...
US-9,607,665 Providing power availability information to memory
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
US-9,606,885 Chained bus method
Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single...
US-9,606,807 Direct communication with a processor internal to a memory device
Devices, systems, and methods of communicating information directly to a sequencer or a buffer in a memory device are provided. In some embodiments,...
US-9,602,436 Switching device
A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through...
US-9,602,080 Phase interpolators and push-pull buffers
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase...
US-9,601,675 Vertical solid-state transducers having backside terminals and associated systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
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