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Patent # Description
US-1,029,7659 Memory devices including capacitor structures having improved area efficiency
Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric...
US-1,029,7640 Cross-point memory with self-defined memory elements
Some embodiments include a memory device having first structures arranged in a first direction and second structures arranged in a second direction. At least...
US-1,029,7612 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-1,029,7611 Transistors and arrays of elevationally-extending strings of memory cells
A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is...
US-1,029,7577 Semiconductor device assembly with heat transfer structure formed from semiconductor material
Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor...
US-1,029,7574 System in package (SIP) with dual laminate interposers
There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is...
US-1,029,7561 Interconnect structures for preventing solder bridging, and associated systems and methods
Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect...
US-1,029,7493 Trench isolation interfaces
The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example...
US-1,029,7340 Switched interface stacked-die memory architecture
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request...
US-1,029,7325 Methods and apparatuses including an asymmetric assist device
Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a...
US-1,029,7309 Methods for independent memory bank maintenance and memory devices and systems employing the same
Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh...
US-1,029,7307 Methods for independent memory bank maintenance and memory devices and systems employing the same
Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh...
US-1,029,7303 Virtual ground sensing circuitry and related devices, systems, and methods for crosspoint ferroelectric memory
A virtual ground sensing circuit includes a sense circuit configured to compare a reference voltage potential to a sense node voltage potential, and virtual...
US-1,029,7298 Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application....
US-1,029,7294 Apparatuses and methods for performing intra-module databus inversion operations
Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module...
US-1,029,7290 Semiconductor devices, and related control logic assemblies, control logic devices, electronic systems, and methods
A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level...
US-1,029,6421 Memory devices and systems with security capabilities
Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller, a main memory...
US-1,029,5590 Probe card with temperature control function, inspection apparatus using the same, and inspection method
A probe card having uniform temperature distribution under control to a desired temperature is provided, so as to provide an inspection apparatus and an...
US-1,029,1439 Decision feedback equalizer
A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and...
US-1,029,0800 Memory cells having a number of conductive diffusion barrier materials and manufacturing methods
Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and...
US-1,029,0799 Magnetic memory cells and semiconductor devices
A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be...
US-1,029,0581 Methods of forming conductive structures including stair step or tiered structures having conductive portions
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via...
US-1,029,0575 Memory devices, semiconductor devices and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
US-1,029,0534 Methods of sealing openings, and methods of forming integrated assemblies
Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include...
US-1,029,0456 Methods of forming and using fuses
Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive...
US-1,029,0422 Capacitors and integrated assemblies which include capacitors
Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar...
US-1,029,0359 Memory refresh methods and apparatuses
Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device...
US-1,029,0351 Systems and methods for internal initialization of a nonvolatile memory
Methods and systems are provided that may include a memory device having a physical nonvolatile memory, a memory space, and a controller. At least a portion of...
US-1,029,0344 Performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,029,0341 Self-reference for ferroelectric memory
Methods, systems, and apparatuses for self-referencing memory cells are described. A reference value for a cell may be created through multiple sense operations...
US-1,029,0336 Methods and apparatuses including command delay adjustment circuit
Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that...
US-1,028,9597 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-1,028,9542 Apparatuses and methods for memory device as a store for block program instructions
The present disclosure includes apparatuses and methods related to a memory device as the store to program instructions. An apparatus comprises a memory device...
US-1,028,9484 Apparatuses and methods for generating probabilistic information with current integration sensing
Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense...
US-1,028,6517 Polishing apparatuses
Some embodiments include an apparatus having a polishing mechanism configured to polish a surface of a wafer. The polishing mechanism converts fresh slurry to...
US-1,028,4186 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-1,028,3705 Memory cells, semiconductor devices including the memory cells, and methods of operation
Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is...
US-1,028,3703 Cross-point memory and methods for forming of the same
The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-1,028,3524 Methods of filling horizontally-extending openings of integrated assemblies
Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first...
US-1,028,3520 Elevationally-extending string of memory cells individually comprising a programmable charge storage transistor...
An elevationally-extending string of memory cells comprises an upper stack elevationally over a lower stack. The upper and lower stacks individually comprise...
US-1,028,3462 Semiconductor devices with post-probe configurability
A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first...
US-1,028,3205 Preemptive idle time read scans
Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory...
US-1,028,3198 Apparatuses and methods of reading memory cells based on response to a test pulse
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of...
US-1,028,3195 Methods of operating a memory with redistribution of received data
Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a...
US-1,028,3188 Data strobe gating
Methods and devices for gating an internal data strobe from an input buffer of a memory device. The gating function occurs after a write operation ceases but...
US-1,028,3187 Apparatuses and methods for providing additional drive to multilevel signals representing data
Apparatuses and methods for providing additional drive to multilevel signals representing data are described. An example apparatus includes a first driver...
US-1,028,3182 Compensating for variations in selector threshold voltages
Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of...
US-1,028,3172 Flexible memory system with a controller and a stack of memory
Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein...
US-1,028,2486 Methods and apparatuses for searching data stored in a memory array using a replicated data pattern
A method includes replicating a data pattern to be searched for, storing the replicated data pattern into a first row of memory cells, and comparing the...
US-1,028,2286 Address mapping using a data unit type that is variable
The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to...
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