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Patent # Description
US-1,024,8592 Interrupted write operation in a serial interface memory with a portion of a memory address
Subject matter disclosed herein relates to read and write processes of a memory device.
US-1,024,8500 Apparatuses and methods for generating probabilistic information with current integration sensing
Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense...
US-1,024,3120 Solid state lighting devices having improved color uniformity and associated methods
Solid state lighting (SSL) devices and methods of manufacturing SSL devices are disclosed herein. In one embodiment, an SSL device comprises a support having a...
US-1,024,2995 Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate...
US-1,024,2989 Polar, chiral, and non-centro-symmetric ferroelectric materials, memory cells including such materials, and...
A ferroelectric memory device includes a plurality of memory cells. Each of the memory cells comprises at least one electrode and a ferroelectric crystalline...
US-1,024,2970 Discontinuous patterned bonds for semiconductor devices and associated systems and methods
Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second...
US-1,024,2901 Systems and methods for wafer alignment
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
US-1,024,2751 Method and apparatus for providing preloaded non-volatile memory content
An embodiment providing one or more improvements includes a memory loading system and method for at least managing testing of a memory unit using a memory test...
US-1,024,2747 Charge loss failure mitigation
Methods of operating a memory include reading a particular grouping of memory cells using a read voltage having a particular voltage level, determining a number...
US-1,024,2746 Shielded vertically stacked data line architecture for memory
Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second...
US-1,024,2744 Boosting channels of memory cells
A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected...
US-1,024,2742 Segmented memory and operation
Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of the plurality of strings is...
US-1,024,2738 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-1,024,2729 Semiconductor device suppressing BTI deterioration
Disclosed herein is a device includes a command generation circuit: that activates first and second command signals, an internal circuit that includes a...
US-1,024,2726 Memory arrays, and methods of forming memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,024,2724 Apparatuses and methods for voltage level control
Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel...
US-1,024,2722 Shifting data in sensing circuitry
The present disclosure includes apparatuses and methods related to shifting data. An example apparatus comprises sensing circuitry including a sense amplifier...
US-1,024,2721 Shifting data in sensing circuitry
The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing...
US-1,024,2718 Flexible memory system with a controller and a stack of memory
Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein...
US-1,024,2239 Systems and methods using single antenna for multiple resonant frequency ranges
A radio frequency device utilizing an antenna having a single antenna structure resonant on multiple resonant frequency ranges. The antenna can be configured to...
US-1,024,1851 Estimation of error correcting performance of low-density parity-check (LDPC) codes
Some embodiments include apparatuses and methods using a low-density parity-check (LDPC) decoding circuit to receive information retrieved from memory cells,...
US-1,024,1185 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-1,023,6301 Methods of forming an array of elevationally-extending strings of memory cells
A method of forming an array of elevationally-extending strings of memory cells comprises forming conductively-doped semiconductor material directly above and...
US-1,023,6127 Apparatuses, multi-chip modules and capacitive chips
Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and...
US-1,023,6072 Electronic device with a fuse read mechanism
A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read...
US-1,023,6052 Current sense amplifiers, memory devices and methods
A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be...
US-1,023,6049 Power reduction for a sensing operation of a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A memory device may leverage non-volatile memory properties of a...
US-1,023,6040 Two-step data-line precharge scheme
Apparatus and methods are disclosed, including an apparatus having a first transistor configured to be coupled to a first bit line, and a control circuit...
US-1,023,6039 Apparatuses and methods for chip identification in a memory package
Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer...
US-1,023,6038 Bank to bank data transfer
The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an...
US-1,023,6037 Data transfer in sensing components
Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example...
US-1,023,6036 Sense amplifier signal boost
Apparatuses for signal boost are disclosed An example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including:...
US-1,023,5627 Adaptive content inspection
Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with...
US-1,022,9923 Integrated assemblies and methods of forming integrated assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with...
US-1,022,9922 Methods of forming memory devices with isolation structures
A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first...
US-1,022,9890 Compensating for memory input capacitance
Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled...
US-1,022,9874 Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays
An array of memory cells individually comprising a capacitor and a transistor comprises, in a first level, alternating columns of digitlines and conductive...
US-1,022,9730 Timing control circuit shared by a plurality of banks
Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first...
US-1,022,9728 Oscillator controlled random sampling method and circuit
Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A...
US-1,022,9727 Apparatus and method for controlling erasing data in ferroelectric memory cells
Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example...
US-1,022,8853 Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and...
US-1,022,6845 Machine tool
A machine tool capable of facilitating a process of mounting a fluid supplying unit to a spindle supporting unit is provided. The machine tool has a rotating...
US-1,022,4313 Interconnect structures with intermetallic palladium joints and associated systems and methods
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
US-1,021,8342 System and method for duty cycle correction
Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives...
US-1,021,8340 Adjustable delay circuit for optimizing timing margin
The present invention relates to timing margin adjustment circuits using adjustable delay circuits. An example adjustable delay circuit may include a signal...
US-1,021,7936 Apparatuses including electrodes having a conductive barrier material and methods of forming same
Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus...
US-1,021,7753 Memory cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
US-1,021,7726 Stacked semiconductor dies including inductors and associated methods
Several embodiments of the present technology are directed to semiconductor devices, systems including semiconductor devices, and methods of making and...
US-1,021,7719 Semiconductor device assemblies with molded support substrates
Semiconductor device assemblies with molded support substrates and associated methods are disclosed herein. In one embodiment, a semiconductor device assembly...
US-1,021,7706 Semiconductor constructions
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
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