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Patent # Description
US-1,011,6829 Information providing system by data relaying application
Information on printer maintenance or an updating of software is notified without giving uncomfortable feeling to a user by an unintentional change of screen...
US-1,011,5715 Methods of making semiconductor device packages and related semiconductor device packages
Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level....
US-1,011,5709 Apparatuses comprising semiconductor dies in face-to-face arrangements
Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a...
US-1,011,5642 Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices
Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The...
US-1,011,5474 Electronic device with a fuse read mechanism
A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read...
US-1,011,5465 Functional data programming in a non-volatile memory
Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function...
US-1,011,5457 Threshold voltage distribution determination by sensing common source line currents
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
US-1,011,5438 Sense amplifier constructions
A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor...
US-1,011,4746 Nonvolatile storage using low latency and high latency memory
Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of...
US-1,011,4647 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-1,011,3113 Removing polysilicon
Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the...
US-1,011,1369 Method and device for automatic storage of tape guides
A system and method for surface mount assembly of PCBs, using an automated pick-and-place machine into which component tapes on reels are fed, uses component...
US-1,011,0256 Apparatuses and methods for staircase code encoding and decoding for storage devices
An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a...
US-1,011,0240 DLL circuit having variable clock divider
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay...
US-1,011,0208 Apparatuses and methods for providing a signal with a differential phase mixer
According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second...
US-1,010,9677 Select device for memory cell applications
The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first...
US-1,010,9640 Transistors having dielectric material containing non-hydrogenous ions and methods of their fabrication
Methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric...
US-1,010,9635 Method of forming semiconductor device including tungsten layer
A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over...
US-1,010,9357 Memory refresh methods and apparatuses
Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device...
US-1,010,9351 Program and read trim setting
A trim set register for a memory device has a plurality of individual trim settings. Each trim setting has a program trim value, a step-up trim value, and a...
US-1,010,9343 Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit...
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each...
US-1,010,9339 Memory devices with selective page-based refresh
Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a...
US-1,010,9327 Apparatuses and methods for controlling data timing in a multi-memory system
Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of...
US-1,010,9325 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-1,010,8684 Data signal mirroring
Methods, devices, and systems for data signal mirroring are described. One or more methods include receiving a particular data pattern on a number of data...
US-1,010,8372 Methods and apparatuses for executing a plurality of queued tasks in a memory
Methods and apparatuses are disclosed for executing a plurality of queued tasks in a memory. One example apparatus includes a memory configured to be coupled to...
US-1,010,7797 Microfluidic apparatus and methods for performing blood typing and crossmatching
Microfluidic cartridges for agglutination reactions are provided. The cartridges include a microfluidic reaction channel with at least two intake channels, one...
US-1,010,3326 Conductive hard mask for memory device formation
Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be...
US-1,010,3290 Ultrathin solid state dies and methods of manufacturing the same
Various embodiments of SST dies and solid state lighting ("SSL") devices with SST dies, assemblies, and methods of manufacturing are described herein. In one...
US-1,010,3196 Methods of forming magnetic memory cells, and methods of forming arrays of magnetic memory cells
Methods of forming a magnetic memory cell are disclosed. The method comprises forming a magnetic cell core material over a substrate, wherein forming the...
US-1,010,3160 Semiconductor structures including dielectric materials having differing removal rates
Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control...
US-1,010,3053 Methods of forming integrated circuitry
Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the...
US-1,010,3038 Thrumold post package with reverse build up hybrid additive structure
Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are...
US-1,010,2914 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected...
US-1,010,2905 Memory cells having a plurality of resistance variable materials
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
US-1,010,1365 Semiconductor module, electrical connector, and inspection apparatus
A semiconductor module includes a control IC mounted on a mounting substrate and a plurality of semiconductor chips mounted on the mounting substrate, and each...
US-1,009,7181 Apparatus and method for standby current control of signal path
Apparatuses and methods for standby current control of a signal path in a semiconductor device are described. An example apparatus includes: first and second...
US-1,009,7169 Method and apparatus for reducing impact of transistor random mismatch in circuits
An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node,...
US-1,009,6748 Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting...
Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are...
US-1,009,6696 Field effect transistors having a fin
An embodiment of a transistor has a semiconductor fin, a dielectric over the semiconductor fin, a control gate over the dielectric, and source/drains in the...
US-1,009,6655 Three dimensional memory array
The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive...
US-1,009,6617 Three-dimensional structured memory devices
A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain...
US-1,009,6579 Thermal pads between stacked semiconductor dies and associated systems and methods
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the...
US-1,009,6576 Semiconductor device assemblies with annular interposers
A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of...
US-1,009,6551 Electronic component of integrated circuitry and a method of forming a conductive via to a region of...
An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface....
US-1,009,6483 Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device...
A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be...
US-1,009,6380 Erase page check
Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an...
US-1,009,6370 Voltage degradation aware NAND array management
Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage...
US-1,009,6365 Erasable block segmentation for memory
Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of...
US-1,009,5574 Apparatuses and methods for comparing a current representative of a number of failing memory cells
Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current...
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