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Patent # Description
US-1,012,7988 Temperature compensation in memory sensing
Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time...
US-1,012,7972 Apparatuses and methods including two transistor-one capacitor memory and for accessing same
Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor...
US-1,012,7971 Systems and methods for memory cell array initialization
Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset...
US-1,012,7969 Memory device command receiving and decoding methods
Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding...
US-1,012,7965 Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory
Apparatuses and methods are disclosed that include ferroelectric memory and for accessing ferroelectric memory. An example method includes increasing a voltage...
US-1,012,7963 Charge sharing between memory cell plates using a conductive path
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to...
US-1,012,7962 Unidirectional spin torque transfer magnetic memory cell structure
Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices...
US-1,012,7954 Quantizing circuits having improved sensing
A system including a processor and a memory device. The memory device includes a memory array having a plurality of memory elements connected to a bit-line and...
US-1,012,6967 Sense operation flags in a memory device
In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell...
US-1,012,6947 Interconnect systems and methods using hybrid memory cube links to send packetized data over different...
System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ...
US-1,012,6357 Methods of testing semiconductor devices comprising a die stack having protruding conductive elements
Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged...
US-1,012,2952 Anti-eclipse circuitry with tracking of floating diffusion reset level
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to...
US-1,012,1966 Semiconductor device structures including silicon-containing dielectric materials
A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals...
US-1,012,1906 Vertical memory strings, and vertically-stacked structures
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels...
US-1,012,1849 Methods of fabricating a semiconductor structure
A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a...
US-1,012,1824 Magnetic structures, semiconductor structures, and semiconductor devices
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The...
US-1,012,1799 Elevationally-extending strings of memory cells individually comprising a programmable charge storage...
A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the...
US-1,012,1766 Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive...
US-1,012,1745 Integrated circuit structures comprising conductive vias and methods of forming conductive vias
A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first...
US-1,012,1739 Multi-die inductors with coupled through-substrate via cores
A semiconductor device comprising first and second dies is provided. The first die includes a first through-substrate via (TSV) extending at least substantially...
US-1,012,1738 Semiconductor constructions
Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor...
US-1,012,1734 Semiconductor device
A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The...
US-1,012,1697 Semiconductor constructions; and methods for providing electrically conductive material within openings
Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a...
US-1,012,1670 Methods of fabricating semiconductor structures
Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate...
US-1,012,1662 Methods of forming structures and methods of decreasing defect density
A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is...
US-1,012,1551 Detecting power loss in NAND memory devices
Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first...
US-1,012,1544 Connecting memory cells to a data line sequentially while applying a program voltage to the memory cells
Programming methods include applying a voltage to a selected access line commonly connected to a plurality of memory cells, and, while the voltage applied to...
US-1,012,1539 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program...
US-1,012,1526 Redundancy array column decoder for memory
Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other...
US-1,012,1523 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-1,012,1521 Read threshold voltage selection
Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a...
US-1,012,0754 Data storage error protection
Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory...
US-1,012,0753 Methods and apparatuses for error correction
Embodiments of the present invention disclose methods and apparatuses for correcting errors in data stored in a solid state device. The solid state device may...
US-1,012,0740 Apparatus and methods for debugging on a memory device
The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory...
US-1,012,0604 Data programming
Apparatuses and methods for performing buffer operations in memory are provided. An example apparatus can include an array of memory cells, a page buffer, and a...
US-1,012,0404 Apparatuses and related methods for staggering power-up of a stack of semiconductor dies
An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an...
US-1,011,6829 Information providing system by data relaying application
Information on printer maintenance or an updating of software is notified without giving uncomfortable feeling to a user by an unintentional change of screen...
US-1,011,5715 Methods of making semiconductor device packages and related semiconductor device packages
Methods of fabricating a semiconductor device package may involve providing a fan out wafer including semiconductor-device-package locations at a base level....
US-1,011,5709 Apparatuses comprising semiconductor dies in face-to-face arrangements
Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a...
US-1,011,5642 Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices
Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The...
US-1,011,5474 Electronic device with a fuse read mechanism
A method of operating an electronic device includes: precharging a fuse read node to an intermediate voltage less than an input voltage, wherein the fuse read...
US-1,011,5465 Functional data programming in a non-volatile memory
Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function...
US-1,011,5457 Threshold voltage distribution determination by sensing common source line currents
Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to...
US-1,011,5438 Sense amplifier constructions
A sense amplifier construction comprises a first n-type transistor and a second n-type transistor above the first n-type transistor. A third p-type transistor...
US-1,011,4746 Nonvolatile storage using low latency and high latency memory
Nonvolatile storage includes first and second memory types with different read latencies. FLASH memory and phase change memory are examples. A first portion of...
US-1,011,4647 Reducing data hazards in pipelined processors to provide high processor utilization
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of...
US-1,011,3113 Removing polysilicon
Methods include exposing polysilicon to an aqueous composition comprising nitric acid, poly-carboxylic acid and ammonium fluoride, and removing a portion of the...
US-1,011,1369 Method and device for automatic storage of tape guides
A system and method for surface mount assembly of PCBs, using an automated pick-and-place machine into which component tapes on reels are fed, uses component...
US-1,011,0256 Apparatuses and methods for staircase code encoding and decoding for storage devices
An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a...
US-1,011,0240 DLL circuit having variable clock divider
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay...
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