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Patent # Description
US-9,418,970 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
US-9,418,968 Semiconductor device including semiconductor chips mounted over both surfaces of substrate
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
US-9,418,926 Package-on-package semiconductor assemblies and methods of manufacturing the same
Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device...
US-9,418,872 Packaged microelectronic components
A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths...
US-9,418,848 Methods of forming patterns with a mask formed utilizing a brush layer
Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first...
US-9,418,735 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,418,734 Multi-function resistance change memory cells and apparatuses including the same
Various embodiments comprise apparatuses including drive circuitry to provide signal pulses of a selected time duration and/or amplitude to a number of memory...
US-9,418,711 Semiconductor memory device having main word lines and sub-word lines
A plurality of memory mats classified into groups selected by bits of a row address, a main word driver for selecting a main word line based on bits of the row...
US-9,418,017 Hot memory block table in a solid state storage device
Solid state storage devices and methods for populating a hot memory block look-up table (HBLT) are disclosed. In one such method, an indication to an accessed...
US-9,417,685 Power management
Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die...
US-9,417,517 Photomask having a blind region including periodical clear portions
A photo mask includes a plurality of dark patterns disposed on a transparent substrate, a first region, a shield region, and a second region. The first region...
US-9,413,535 Critical security parameter generation and exchange system and method for smart-card memory modules
A storage device contains a smart-card device and a memory device, which is connected to a controller. The storage device may be used in the same manner as a...
US-9,413,338 Apparatuses, methods, and circuits including a duty cycle adjustment circuit
Apparatuses, methods, and duty cycle correction circuits are described. An example apparatus includes a duty cycle correction (DCC) adjustment circuit...
US-9,412,941 Phase change memory cell with self-aligned vertical heater and low resistivity interface
A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change...
US-9,412,936 Memory cells, methods of forming memory cells and methods of forming memory arrays
Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material...
US-9,412,779 Method, apparatus and system providing a storage gate pixel with high dynamic range
A method, apparatus and system are described providing a high dynamic range pixel. An integration period has multiple sub-integration periods during which...
US-9,412,706 Engineered carrier wafers
Apparatuses and methods for reducing the warp of semiconductor wafer stacks during manufacturing are disclosed. An engineered carrier wafer is disclosed. The...
US-9,412,677 Computer systems having an interposer including a flexible material
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-9,412,675 Interconnect structure with improved conductive properties and associated systems and methods
Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive...
US-9,412,594 Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a...
US-9,412,591 Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The...
US-9,412,472 Determining soft data from a hard read
Apparatuses and methods involving the determination of soft data from hard reads are provided. One example method can include determining, using a hard read, a...
US-9,412,451 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A...
US-9,412,421 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines...
US-9,411,694 Correcting recurring errors in memory
The present disclosure includes apparatuses and methods for correcting recurring errors in memory. A number of embodiments include determining whether a first...
US-9,411,684 Low density parity check circuit
Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of...
US-9,411,675 Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using...
US-9,411,538 Memory systems and methods for controlling the timing of receiving read data
Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A...
US-9,411,529 Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes mapping a data pattern to a...
US-9,409,030 Neural stimulator system
An implantable neural stimulator includes one or more electrodes, a dipole antenna, and one or more circuits and does not include an internal power source. The...
US-9,409,029 Remote RF power system with low profile transmitting antenna
An antenna assembly includes: an antenna including: a metal signal layer having a radiating surface; and a feed port; and a waveguide surrounding the antenna...
US-9,407,039 Interconnection systems
Interconnection systems are shown that include communication contacts, and a guide. Configurations are shown with a guide that locates a male portion with...
US-9,406,881 Memory cells having a heater electrode formed between a first storage material and a second storage material...
The present disclosure includes memory cells and methods of forming the same. The memory cells disclosed herein can include a heater electrode formed between a...
US-9,406,880 Resistive memory having confined filament formation
Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon...
US-9,406,878 Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells,...
Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across...
US-9,406,874 Magnetic memory cells and methods of formation
Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress...
US-9,406,660 Stacked semiconductor die assemblies with die support members and associated systems and methods
Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,406,623 Electromagnetic shield and associated methods
Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material,...
US-9,406,606 Semiconductor device having a reduced area and enhanced yield
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power...
US-9,406,404 Column redundancy system for a memory array
A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to...
US-9,406,389 Electronically coupling a data line to a source for biasing regardless of states of memory cells coupled to the...
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory...
US-9,406,388 Memory area protection system and methods
In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from...
US-9,406,384 Matching semiconductor circuits
Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between...
US-9,406,363 Memory apparatus and system with shared wordline decoder
A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels,...
US-9,406,362 Memory tile access and selection patterns
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile...
US-9,406,357 Data capture system and method, and memory controllers and devices
Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system...
US-9,406,353 Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential...
US-9,405,874 Time-domain signal generation
Methods and apparatuses disclose various embodiments of time-domain signal generation. In one embodiment a method includes receiving an input waveform having a...
US-9,405,859 Using do not care data with feature vectors
Methods for storing a feature vector, as well as related comparison units and systems. One such method involves programming a string of memory cells of memory...
US-9,405,721 Apparatuses and methods for performing a databus inversion operation
Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in...
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