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Tunnel and gate oxide comprising nitrogen for use with a semiconductor
device and a process for forming the device
A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor...
Multi-resistive integrated circuit memory
A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a...
Multi-layer structures for parameter measurement
Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay...
Methods of forming fluorine doped insulating materials
In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing...
Semiconductor fabrication processes
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is...
Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit...
Non-equal threshold voltage ranges in MLC NAND
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
Devices and systems including the bit lines and bit line contacts
A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases...
Methods of fabrication for flip-chip image sensor packages
The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the...
Semiconductor processing methods of transferring patterns from patterned
photoresists to materials
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first...
Methods of forming capacitor structures
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger...
Programmable resistance memory devices and systems using the same and
methods of forming the same
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first...
Apparatus and method for depositing and reflowing solder paste on a
Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and...
User selectable banks for DRAM
A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by...
Output buffer strength trimming
Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage...
Scalable high density non-volatile memory cells in a contactless memory
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion...
Methods of forming capacitors
A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising...
Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach...
Well for CMOS imager and method of formation
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically...
Filter cloth connector
Apparatuses and methods for making and using a filter cloth assembly are described. A filter cloth assembly can have a liquid permeable filtering medium attached...
System for locating conductive sphere utilizing screen and hopper of
System for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads....
Method of forming a magnetic random access memory element
A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a...
Memory system for data storage and retrieval
According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system,...
Method and apparatus for self-timed data ordering for multi-data rate
memories and system incorporating same
A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during...
Alignment of instructions and replies across multiple devices in a
cascaded system, using buffers of...
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the...
Current mode memory apparatus, systems, and methods
Some embodiments include a first circuit to receive input signals and to drive signals at first circuit output nodes, and a second circuit to receive at least a...
Adjusting programming or erase voltage pulses in response to the number of
programming or erase failures
Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to...
Memory in logic cell
Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate,...
M+N bit programming and M+L bit read for M bit memory cells
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage...
Couplings within memory devices and methods
Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer...
On-die anti-resonance structure for integrated circuit
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to...
Method of and apparatus for reducing settling time of a switched capacitor
A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an...
Semiconductor device assemblies and packages with edge contacts and
sacrificial substrates and other...
A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which...
Microelectronic devices having a curved surface and methods for
manufacturing the same
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a...
One-transistor composite-gate memory
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
Conductive structures for microfeature devices and methods for fabricating
Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein....
Protection in integrated circuits
A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a...
Methods of forming a resistance variable element
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one...
Program controlled embedded-DRAM-DSP having improved instruction set
An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register...
Temperature compensation of memory signals using digital signals
A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates...
On-chip temperature sensor
A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant...
Erase operation in a flash drive memory
A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the...
Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates...
Single latch data circuit in a multiple level call non-volatile memory
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a...