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Patent # Description
US-7,656,166 Multilayer wiring board and method for testing the same
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which...
US-7,656,049 CMOS device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-7,656,012 Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices...
A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The...
US-7,656,006 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor...
US-7,655,973 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-7,655,968 Semiconductor devices
A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during...
US-7,655,508 Overmolding encapsulation process and encapsulated article made therefrom
A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first...
US-7,655,507 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,655,500 Packaged microelectronic devices and methods for packaging microelectronic devices
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
US-7,655,387 Method to align mask patterns
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming...
US-7,655,384 Methods for reducing spherical aberration effects in photolithography
Methods to at least partially compensate for photoresist-induced spherical aberration that occurs during mask imaging used for photolithographic processing of...
US-7,655,095 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
US-7,652,703 Dual panel pixel readout in an imager
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual...
US-7,652,669 Animation packager for an on-line book
A system for creating an on-line book with an animated cover. The system includes an animation program for inserting an animation sequence at the beginning of an...
US-7,652,495 Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using...
Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment...
US-7,652,365 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,651,956 Process for fabricating films of uniform properties on semiconductor devices
A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying...
US-7,651,951 Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns....
US-7,651,911 Memory transistor and methods
A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At...
US-7,651,910 Methods of forming programmable memory devices
The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed...
US-7,650,588 Methods and systems for pattern generation based on multiple forms of design data
In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write...
US-7,650,541 Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
US-7,649,783 Delayed activation of selected wordlines in memory
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation...
US-7,649,316 Assemblies for plasma-enhanced treatment of substrates
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-7,649,201 Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels
An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised...
US-7,649,145 Compliant spring contact structures
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a...
US-7,648,926 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,648,915 Methods of forming semiconductor constructions, and methods of recessing materials within openings
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.8. The recessed...
US-7,648,900 Vias having varying diameters and fills for use with a semiconductor device and methods of forming...
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second...
US-7,648,873 Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
US-7,648,872 Methods of forming DRAM arrays
Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include...
US-7,648,856 Methods for attaching microfeature dies to external devices
Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other...
US-7,648,835 System and method for heating, cooling and heat cycling on microfluidic device
An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and...
US-7,648,806 Phase shift mask with two-phase clear feature
Systems and methods are provided for use in photolithography. In one embodiment, a reticle is provided that comprises a phase shift and transmission control...
US-7,647,886 Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from...
Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one...
US-7,647,569 Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient...
Systems and methods are disclosed for organizing layout data. A layout database is analyzed to determine a statistical distribution of cells within the layout...
US-7,646,919 Graphics engine for high precision lithography
The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability...
US-7,646,654 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
US-7,646,407 Digital exposure circuit for an image sensor
Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the...
US-7,646,229 Method of output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,646,213 On-die system and method for controlling termination impedance of memory device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a...
US-7,646,102 Wafer level pre-packaged flip chip systems
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment,...
US-7,646,099 Self-aligned, integrated circuit contact
Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer...
US-7,646,075 Microelectronic imagers having front side contacts
Microelectronic imager assemblies with front side contacts and methods for fabricating such microelectronic imager assemblies are disclosed herein. In one...
US-7,646,053 Memory cell storage node length
Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first...
US-7,646,016 Method for automated testing of the modulation transfer function in image sensors
A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the...
US-7,646,007 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,645,671 Recessed access device for a memory
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a...
US-7,645,635 Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and...
A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture...
US-7,645,344 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
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