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Patent # Description
US-7,648,926 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,648,915 Methods of forming semiconductor constructions, and methods of recessing materials within openings
Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C.sub.4F.sub.6 and C.sub.4F.sub.8. The recessed...
US-7,648,900 Vias having varying diameters and fills for use with a semiconductor device and methods of forming...
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second...
US-7,648,873 Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
US-7,648,872 Methods of forming DRAM arrays
Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include...
US-7,648,856 Methods for attaching microfeature dies to external devices
Methods for attaching microfeature dies to external devices are disclosed. The external devices can include other microfeature dies, support members or other...
US-7,648,835 System and method for heating, cooling and heat cycling on microfluidic device
An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and...
US-7,648,806 Phase shift mask with two-phase clear feature
Systems and methods are provided for use in photolithography. In one embodiment, a reticle is provided that comprises a phase shift and transmission control...
US-7,647,886 Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from...
Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one...
US-7,647,569 Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient...
Systems and methods are disclosed for organizing layout data. A layout database is analyzed to determine a statistical distribution of cells within the layout...
US-7,646,919 Graphics engine for high precision lithography
The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability...
US-7,646,654 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
US-7,646,407 Digital exposure circuit for an image sensor
Automatic exposure adjusting device considers the image on a pixel-by-pixel basis. Each pixel is characterized according to its most significant bits. After the...
US-7,646,229 Method of output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,646,213 On-die system and method for controlling termination impedance of memory device data bus terminals
A system for controlling the termination impedance of memory device data bus terminals is fabricated on the same die as the memory device. The system includes a...
US-7,646,102 Wafer level pre-packaged flip chip systems
Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment,...
US-7,646,099 Self-aligned, integrated circuit contact
Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer...
US-7,646,075 Microelectronic imagers having front side contacts
Microelectronic imager assemblies with front side contacts and methods for fabricating such microelectronic imager assemblies are disclosed herein. In one...
US-7,646,053 Memory cell storage node length
Methods, devices, and systems for a memory cell are provided. One embodiment includes a memory cell with a storage node separated from a body region by a first...
US-7,646,016 Method for automated testing of the modulation transfer function in image sensors
A method for automatically measuring the modulation transfer function of an imager is disclosed. A opaque mask is placed over selected columns and rows of the...
US-7,646,007 Silver-selenide/chalcogenide glass stack for resistance variable memory
The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics....
US-7,645,671 Recessed access device for a memory
Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a...
US-7,645,635 Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and...
A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture...
US-7,645,344 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
US-7,644,853 Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux
A method of attaching solder balls to a BGA package using a ball pickup tool is disclosed. An array of solder balls is formed on a first substrate for...
US-7,644,253 Memory hub with internal cache and/or memory access prediction
A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory ("SDRAM") devices. The memory hub...
US-7,644,240 Memory device controller
A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core...
US-7,644,235 Device and method for configuring a cache tag in accordance with burst length
In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not...
US-7,643,984 Method and system for selecting compatible processors to add to a multiprocessor computer
A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program...
US-7,643,370 Memory device having conditioning output data
Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing...
US-7,643,359 Clock generating circuit with multiple modes of operation
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock...
US-7,643,343 NAND string with a redundant memory cell
The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled...
US-7,643,333 Process for erasing chalcogenide variable resistance memory bits
A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate...
US-7,642,827 Apparatus and method for multi-phase clock generation
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second...
US-7,642,651 Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via,...
US-7,642,643 Apparatus for molding a semiconductor die package with enhanced thermal conductivity
A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back...
US-7,642,616 Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device
A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor...
US-7,642,591 Multi-resistive integrated circuit memory
A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a...
US-7,642,550 Multi-layer structures for parameter measurement
Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay...
US-7,642,204 Methods of forming fluorine doped insulating materials
In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing...
US-7,642,196 Semiconductor fabrication processes
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,642,157 Method for enhancing electrode surface area in DRAM cell capacitors
Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is...
US-D607,437 Speaker
US-7,640,465 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,640,413 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit...
US-7,639,532 Non-equal threshold voltage ranges in MLC NAND
Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data...
US-7,639,530 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,...
US-7,639,528 Nanocrystal write once read only memory for archival storage
Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide...
US-7,639,090 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,638,878 Devices and systems including the bit lines and bit line contacts
A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases...
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