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| Patent # | Description |
|---|---|
| US-7,668,000 |
Method and apparatus providing a cross-point memory array using a variable
resistance memory cell and capacitance The invention relates to a method and apparatus providing a memory cell array in which each resistance memory cell is connected in series to a capacitive... |
| US-7,667,632 |
Quantizing circuits for semiconductor devices An electronic device that includes an internal data storage location coupled to an electrical conductor and a quantizing circuit coupled to the internal data... |
| US-7,667,472 |
Probe assembly, method of producing it and electrical connecting apparatus A probe assembly for use in electrical measurement of a device under test. The probe assembly comprises a plate-like probe base plate with bending deformation... |
| US-7,667,260 |
Nanoscale floating gate and methods of formation A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first... |
| US-7,667,258 |
Double-sided container capacitors using a sacrificial layer Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is... |
| US-7,667,234 |
High density memory array having increased channel widths A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that... |
| US-7,666,801 |
Systems and methods for forming metal oxides using metal compounds
containing aminosilane ligands A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a... |
| US-7,666,797 |
Methods for forming semiconductor constructions, and methods for
selectively etching silicon nitride relative... The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for... |
| US-7,666,788 |
Methods for forming conductive vias in semiconductor device components A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the... |
| US-7,666,776 |
Methods of forming conductive structures The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material... |
| US-7,666,578 |
Efficient pitch multiplication process Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated... |
| US-7,664,999 |
Real time testing using on die termination (ODT) circuit A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is... |
| US-7,664,216 |
Digital frequency locked delay line A device includes a signal generator having a delay locked circuit for providing a of output signals based on an input signal. The output signals have a fixed... |
| US-7,663,952 |
Capacitor supported precharging of memory digit lines Circuits and methods are provided for precharging pairs of memory digit lines. The final precharge voltage of the digit lines is different from the average of... |
| US-7,663,934 |
Program method with optimized voltage level for flash memory A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the... |
| US-7,663,930 |
Programming a non-volatile memory device A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial... |
| US-7,663,926 |
Cell deterioration warning apparatus and method Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate... |
| US-7,663,925 |
Method and apparatus for programming flash memory A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths... |
| US-7,663,901 |
Techniques for implementing accurate device parameters stored in a
database Memory modules and methods for fabricating and implementing memory modules wherein unique device parameters corresponding to specific memory devices on the... |
| US-7,663,232 |
Elongated fasteners for securing together electronic components and
substrates, semiconductor device assemblies... Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion... |
| US-7,663,224 |
Semiconductor BGA package having a segmented voltage plane A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive... |
| US-7,663,206 |
Interposer including at least one passive element at least partially
defined by a recess formed therein, system... An interposer for assembly with a semiconductor die and methods of manufacture are disclosed. The interposer may include at least one passive element at least... |
| US-7,663,137 |
Phase change memory cell and method of formation A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase... |
| US-7,663,133 |
Memory elements having patterned electrodes and method of forming the same A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes... |
| US-7,662,729 |
Atomic layer deposition of a ruthenium layer to a lanthanide oxide
dielectric layer Electronic apparatus and methods of forming the electronic apparatus include a conductive layer having a layer of ruthenium in contact with a lanthanide oxide... |
| US-7,662,719 |
Slurry for use in polishing semiconductor device conductive structures
that include copper and tungsten and... A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method... |
| US-7,662,718 |
Trim process for critical dimension control for integrated circuits Methods of etching substrates employing a trim process for critical dimension control for integrated circuits are disclosed. In one embodiment, the method of... |
| US-7,662,701 |
Gettering of silicon on insulator using relaxed silicon germanium
epitaxial proximity layers One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this... |
| US-7,662,693 |
Lanthanide dielectric with controlled interfaces Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer... |
| US-7,662,658 |
Photodiode with ultra-shallow junction for high quantum efficiency CMOS
image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow... |
| US-7,662,649 |
Methods for assessing alignments of substrates within deposition
apparatuses; and methods for assessing... The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having... |
| US-7,662,648 |
Integrated circuit inspection system Methods and systems that include a nanotube used as an emitter in the testing and fabrication of integrated circuits. The nanotube emits a signal to a substrate.... |
| US-7,662,299 |
Nanoimprint lithography template techniques for use during the fabrication
of a semiconductor device and... A method for forming a template useful for nanoimprint lithography comprises forming at least one pillar which provides a topographic feature extending from a... |
| US-7,660,708 |
S-matrix technique for circuit simulation A methodology for combining two or more S-parameter blocks/matrices (each representing a circuit or network, or the interconnection between a circuit or network)... |
| US-7,660,187 |
Method and apparatus for initialization of read latency tracking circuit
in high-speed DRAM A method of controlling the output of data from a memory device includes deriving from an external clock signal a read clock and a control clock for operating an... |
| US-7,660,172 |
Method and apparatus for synchronizing data from memory arrays According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for... |
| US-7,660,158 |
Programming method to reduce gate coupling interference for non-volatile
memory A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or... |
| US-7,660,144 |
High-performance one-transistor memory cell A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential... |
| US-7,659,727 |
Multilayer wiring board and method for testing the same A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of... |
| US-7,659,630 |
Interconnect structures with interlayer dielectric The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially... |
| US-7,659,612 |
Semiconductor components having encapsulated through wire interconnects
(TWI) A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact.... |
| US-7,659,560 |
Transistor structures A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill... |
| US-7,659,211 |
Method and apparatus for fabricating a memory device with a dielectric
etch stop layer The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect.... |
| US-7,659,210 |
Nano-crystal etch process A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing... |
| US-7,659,208 |
Method for forming high density patterns Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is... |
| US-7,659,205 |
Amorphous carbon-based non-volatile memory A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A... |
| US-7,659,181 |
Sub-micron space liner and filler process A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an... |
| US-7,659,161 |
Methods of forming storage nodes for a DRAM array The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array... |
| US-7,659,152 |
Localized biasing for silicon on insulator structures A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned... |
| US-7,659,151 |
Flip chip with interposer, and methods of making same A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller... |
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