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| Patent # | Description |
|---|---|
| US-7,961,522 |
Method and system for minimizing number of programming pulses used to
program rows of non-volatile memory cells A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during... |
| US-7,961,518 |
Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer... |
| US-7,961,517 |
Program and read trim setting A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device... |
| US-7,961,507 |
Non-volatile memory with resistive access component Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of... |
| US-7,961,506 |
Multiple memory cells with rectifying device Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,... |
| US-7,961,488 |
Method for modifying data more than once in a multi-level cell memory
location within a memory array A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a... |
| US-7,961,341 |
Print system, print data supplying device, and method for supplying print
data to printer A print system includes: a printer; and a print data supplying device. The print data supplying device includes: a print data supplying unit that supplies the... |
| US-7,961,292 |
Sub-resolution assist devices and methods Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask... |
| US-7,961,127 |
Variable gain stage having same input capacitance regardless of the stage
gain A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes... |
| US-7,961,019 |
Delay-lock loop and method adapting itself to operate over a wide
frequency range A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes... |
| US-7,960,988 |
Contactor for electrical test, electrical connecting apparatus using the
same, and method for manufacturing... An electrical test contactor comprises a contactor main body including a plate-shaped attachment portion extending in the up-down direction, a plate-shaped arm... |
| US-7,960,829 |
Support structure for use in thinning semiconductor substrates and for
supporting thinned semiconductor substrates A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the... |
| US-7,960,813 |
Programmable resistance memory devices and systems using the same and
methods of forming the same A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first... |
| US-7,960,803 |
Electronic device having a hafnium nitride and hafnium oxide film The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of... |
| US-7,960,797 |
Semiconductor devices including fine pitch arrays with staggered contacts A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one... |
| US-7,960,291 |
Porous organosilicate layers, and vapor deposition systems and methods for
preparing same The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous... |
| US-7,959,975 |
Methods of patterning a substrate A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is... |
| US-7,958,491 |
Command line output redirection In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method... |
| US-7,958,439 |
Defective memory block remapping method and system, and memory device and
processor-based system using same A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an... |
| US-7,957,215 |
Method and apparatus for generating temperature-compensated read and
verify operations in flash memories Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable... |
| US-7,957,214 |
Adjustable voltage regulator for providing a regulated output voltage Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator... |
| US-7,957,206 |
Read circuitry for an integrated circuit having memory cells and/or a
memory cell array, and method of... An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each... |
| US-7,957,198 |
Verifying an erase threshold in a memory device In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory... |
| US-7,957,196 |
Method of programming memory cells of series strings of memory cells Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after... |
| US-7,957,182 |
Memory cell having nonmagnetic filament contact and methods of operating
and fabricating the same A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes... |
| US-7,957,055 |
Pattern generator The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a... |
| US-7,956,914 |
Imager methods, apparatuses, and systems providing a skip mode with a wide
dynamic range operation Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an... |
| US-7,956,912 |
Active pixel sensor with mixed analog and digital signal integration An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,... |
| US-7,956,685 |
Adaptive operational transconductance amplifier load compensation A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The... |
| US-7,956,673 |
Variable stage charge pump and method for providing boosted output voltage An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage.... |
| US-7,956,648 |
Output driver robust to data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may... |
| US-7,956,443 |
Through-wafer interconnects for photoimager and memory wafers A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making... |
| US-7,956,426 |
Lanthanide dielectric with controlled interfaces Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer... |
| US-7,956,416 |
Integrated circuitry Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material... |
| US-7,956,402 |
Double-doped polysilicon floating gate The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method... |
| US-7,955,976 |
Methods of forming semiconductor structures The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an... |
| US-7,955,946 |
Methods of determining x-y spatial orientation of a semiconductor
substrate comprising an integrated circuit,... The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a... |
| US-7,955,935 |
Non-volatile memory cell devices and methods A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots,... |
| US-7,955,917 |
Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate
methods A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are... |
| US-7,955,898 |
Packaged microelectronic devices and methods for manufacturing packaged
microelectronic devices Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a... |
| US-7,955,836 |
Microfluidic mixing and analytical apparatus Disclosed herein is a device comprising a pair of bellows pumps configured for efficient mixing at a microfluidic scale. By moving a fluid sample and particles... |
| US-7,955,764 |
Methods to make sidewall light shields for color filter array Methods of forming color filters having a light blocking material therebetween. A color filter is formed such that a trench is defined between a color filter... |
| US-7,954,029 |
System, apparatus, and method for memory built-in self testing using
microcode sequencers Apparatuses, systems, and methods are disclosed for performing Built-In Self Tests (BIST) on memories. One such BIST includes loading microcode instructions... |
| US-7,954,004 |
Systems and methods for retrieving data Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques... |
| US-7,953,954 |
Flash storage partial page caching Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device... |
| US-7,953,579 |
Jittery signal generation with discrete-time filtering The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the... |
| US-7,952,952 |
Reduction of fusible links and associated circuitry on memory dies The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among... |
| US-7,952,936 |
Program-verify method Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory... |
| US-7,952,927 |
Adjusting program and erase voltages in a memory device A method and apparatus for adjusting threshold program and erase voltages in a memory array, such as a floating gate memory array, for example. A method... |
| US-7,952,924 |
NAND memory device and programming methods A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines... |
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