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| Patent # | Description |
|---|---|
| US-7,759,053 |
Methods of fabricating integrated circuitry The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a... |
| US-7,757,385 |
System for fabricating semiconductor components with through wire
interconnects A method for fabricating a semiconductor component with a through wire interconnect includes the step of providing a substrate having a circuit side, a back... |
| US-7,757,061 |
System and method for decoding commands based on command signals and
operating state A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on... |
| US-7,755,940 |
Method, apparatus, and system for erasing memory Methods, apparatus, and systems may operate such as to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. One... |
| US-7,755,939 |
System and devices including memory resistant to program disturb and
methods of using, making, and operating... Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of... |
| US-7,755,684 |
Row driver circuitry for imaging devices and related method of operation Row drivers as a part of an image sensor device include circuitry for supplying a plurality of signals with an increased voltage and enhanced reliability to a... |
| US-7,755,657 |
Method for high precision printing of patterns The present invention includes a method to print patterns with improved edge acuity. The method for printing fine patterns comprises the actions of: providing an... |
| US-7,755,570 |
Microdisplay and interface on a single chip A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same... |
| US-7,755,404 |
Delay locked loop circuit and method Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a... |
| US-7,755,385 |
Method for operating an electronic device with reduced pin capacitance A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively... |
| US-7,755,316 |
Moving member movement control apparatus, moving member movement control
method and machine tool movement... A movement control apparatus for a moving member, includes: a drive unit that moves a moving member by rapid traverse on a first axis and a second axis... |
| US-7,755,204 |
Stacked die module including multiple adhesives that cure at different
temperatures A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked... |
| US-7,755,183 |
Wiring board, method of manufacturing the same, and semiconductor device According to this invention, a wiring board includes a conductive pattern formed from leads each of which is formed on an organic layer and has a thickness t... |
| US-7,755,119 |
Method and apparatus for reducing imager floating diffusion leakage An imager having reduced floating diffusion leakage and a mechanism for improving the storing of collected charge is described. A polysilicon contact is provided... |
| US-7,754,618 |
Method of forming an apparatus having a dielectric containing cerium oxide
and aluminum oxide A dielectric layer including cerium oxide and aluminum oxide acting as a single dielectric layer, and a method of fabricating such a dielectric layer, produces a... |
| US-7,754,612 |
Methods and apparatuses for removing polysilicon from semiconductor
workpieces Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad... |
| US-7,754,576 |
Method of forming inside rough and outside smooth HSG electrodes and
capacitor structure A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a... |
| US-7,754,532 |
High density chip packages, methods of forming, and systems including same Methods and devices for multi-chip stacks are shown. A method is shown that assembles multiple chips into stacks by stacking wafers prior to dicing into... |
| US-7,754,531 |
Method for packaging microelectronic devices Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes... |
| US-7,754,522 |
Phase change memory structures and methods Methods, devices, and systems associated with phase change memory structures are described herein. One or more embodiments of the present disclosure can reduce... |
| US-7,754,399 |
Methods of forming reticles The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes... |
| US-7,754,395 |
Methods of forming and using reticles Some embodiments include methods of treating reticles to provide backside masking across regions of the reticle to compensate for problems occurring during... |
| US-7,753,693 |
Contacts and electrical connecting apparatus using the same An electrical connecting apparatus uses a plurality of contacts each of which includes: a principal portion having an outer face curved and directed to a... |
| US-RE41,441 |
Output buffer having inherently precise data masking A maskable data output buffer includes an output stage receiving data signals from a data coder. The signals output from the data coder are normally... |
| US-7,752,381 |
Version based non-volatile memory translation layer A non-volatile memory and erase block/data block/sector/cluster update and address translation scheme utilizing a version number is detailed that enhances data... |
| US-7,751,634 |
Compression system for integrated sensor devices An imaging system incorporating adaptive compression which includes determining linear predictive differential residuals from an imager array pixel row. The... |
| US-7,751,263 |
Data retention kill function Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the... |
| US-7,751,260 |
Memory device having strobe terminals with multiple functions A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device... |
| US-7,751,253 |
Analog sensing of memory cells with a source follower driver in a
semiconductor memory device Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One... |
| US-7,751,246 |
Charge loss compensation during programming of a memory device A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful... |
| US-7,751,245 |
Programming sequence in NAND memory An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source... |
| US-7,751,242 |
NAND memory device and programming methods A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines... |
| US-7,751,236 |
MEM suspended gate non-volatile memory A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing... |
| US-7,751,228 |
Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site... |
| US-7,750,449 |
Packaged semiconductor components having substantially rigid support
members and methods of packaging... Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member... |
| US-7,750,395 |
Scalable Flash/NV structures and devices with extended endurance Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of... |
| US-7,750,389 |
NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function... |
| US-7,750,379 |
Metal-substituted transistor gates One aspect of this disclosure relates to an integrated circuit structure. An integrated circuit structure embodiment includes a substrate, a gate dielectric over... |
| US-7,750,344 |
Doped aluminum oxide dielectrics Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation... |
| US-7,749,899 |
Microelectronic workpieces and methods and systems for forming
interconnects in microelectronic workpieces Methods and systems for forming electrical interconnects through microelectronic workpieces are disclosed herein. One aspect of the invention is directed to a... |
| US-7,749,887 |
Methods of fluxless micro-piercing of solder balls, and resulting devices A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material,... |
| US-7,749,885 |
Semiconductor processing methods, methods of forming contact pads, and
methods of forming electrical... Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel... |
| US-7,749,882 |
Packaged microelectronic devices and methods for manufacturing packaged
microelectronic devices Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes... |
| US-7,749,879 |
ALD of silicon films on germanium The use of atomic layer deposition (ALD) to form a semiconductor structure of a silicon film on a germanium substrate is disclosed. An embodiment includes a... |
| US-7,749,860 |
Method for forming a self-aligned T-shaped isolation trench The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical... |
| US-7,749,849 |
Methods of selectively oxidizing semiconductor structures, and structures
resulting therefrom Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas... |
| US-7,749,848 |
Band-engineered multi-gated non-volatile memory device with enhanced
attributes Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate... |
| US-7,749,837 |
High coupling memory cell A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric... |
| US-7,749,808 |
Stacked microelectronic devices and methods for manufacturing
microelectronic devices Stacked microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such microelectronic device can... |
| US-7,749,786 |
Methods of forming imager systems Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for... |
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