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| Patent # | Description |
|---|---|
| US-7,787,174 |
Pattern generator The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical... |
| US-7,786,803 |
Operational transconductance amplifier (OTA) Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include... |
| US-7,786,605 |
Stacked semiconductor components with through wire interconnects (TWI) A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact.... |
| US-7,786,522 |
Method for forming memory cell and device A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to... |
| US-7,786,516 |
Discrete trap non-volatile multi-functional memory device A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of... |
| US-7,786,016 |
Methods of uniformly removing silicon oxide and a method of removing a
sacrificial oxide A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one... |
| US-7,785,998 |
Methods of forming dispersions of nanoparticles, and methods of forming
flash memory cells Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the... |
| US-7,785,978 |
Method of forming memory cell using gas cluster ion beams A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the... |
| US-7,785,976 |
Method of forming a memory device incorporating a resistance-variable
chalcogenide element A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and... |
| US-7,785,962 |
Methods of forming a plurality of capacitors A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises... |
| US-7,785,961 |
Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for... |
| US-7,783,934 |
Program failure recovery A program failure is detected during programming of a memory device. When the program failure is detected, a transfer of the contents of a register of the memory... |
| US-7,782,677 |
NAND memory device column charging Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on... |
| US-7,782,674 |
Sensing of memory cells in NAND flash An analog voltage NAND architecture non-volatile memory data read/verify process and circuits is described that senses analog voltages in non-volatile cells... |
| US-7,781,877 |
Packaged integrated circuit devices with through-body conductive vias, and
methods of making same A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at... |
| US-7,781,875 |
Techniques for packaging multiple device components Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a... |
| US-7,781,868 |
Semiconductor components having through interconnects and backside
redistribution conductors A semiconductor component includes a semiconductor substrate having a circuit side with integrated circuits and substrate contacts and a back side, a plurality... |
| US-7,781,860 |
Semiconductor constructions, and electronic systems The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can... |
| US-7,781,818 |
Semiconductor constructions containing tubular capacitor storage nodes,
and retaining structures along portions... The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention... |
| US-7,779,212 |
Method and apparatus for sending data from multiple sources over a
communications bus In a memory system, multiple memory modules communicate over a bus. Each memory module includes a hub and at least one memory storage unit. The hub receives... |
| US-7,778,812 |
Selecting data to verify in hardware device model simulation test
generation Embodiments of the present invention provide a method for generating write and read commands used to test hardware device models. The method is able to generate... |
| US-7,778,092 |
Memory system and method having volatile and non-volatile memory devices
at same hierarchical level A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer... |
| US-7,778,086 |
Erase operation control sequencing apparatus, systems, and methods Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate.... |
| US-7,778,039 |
Substrates, systems, and devices including structures for suppressing
power and ground plane noise, and methods... Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress... |
| US-7,777,287 |
System and apparatus providing analytical device based on solid state
image sensor An analytical system-on-a-chip can be used as an analytical imaging device, for example, for detecting the presence of a chemical compound. A layer of analytical... |
| US-7,777,264 |
Random access memory device utilizing a vertically oriented select
transistor A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor... |
| US-7,776,765 |
Tantalum silicon oxynitride high-k dielectrics and metal gates Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic... |
| US-7,776,762 |
Zirconium-doped tantalum oxide films Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer is formed of one or more monolayers of... |
| US-7,776,749 |
Methods of forming semiconductor constructions The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth... |
| US-7,776,744 |
Pitch multiplication spacers and methods of forming the same Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the... |
| US-7,776,715 |
Reverse construction memory cell A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a... |
| US-7,776,683 |
Integrated circuit fabrication A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a... |
| US-7,776,652 |
Methods for stacking wire-bonded integrated circuit dice on flip-chip
bonded integrated circuit dice An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a... |
| US-7,776,647 |
Semiconductor components and methods of fabrication with circuit side
contacts, conductive vias and backside... A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts... |
| US-7,775,710 |
DRAM temperature management system A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a... |
| US-7,774,683 |
Erasure pointer error correction Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in... |
| US-7,774,559 |
Method and system for terminating write commands in a hub-based memory
system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write... |
| US-7,774,536 |
Power up initialization for memory A memory device is described that enhances initialization of the memory device. In the prior art, initialization of synchronous Flash memory requires the release... |
| US-7,773,492 |
Method and apparatus providing high density data storage A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data... |
| US-7,773,441 |
Memory malfunction prediction system and method A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of... |
| US-7,773,418 |
Non-volatile memory with both single and multiple level cells Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed... |
| US-7,773,412 |
Method and apparatus for providing a non-volatile memory with reduced cell
capacitive coupling A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted,... |
| US-7,772,908 |
Voltage and temperature compensation delay system and method A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input... |
| US-7,772,680 |
Arrangements of fuse-type constructions The invention includes semiconductor fuse arrangements containing an electrically conductive plate over and in electrical contact with a plurality of... |
| US-7,772,672 |
Semiconductor constructions The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom... |
| US-7,772,635 |
Non-volatile memory device with tensile strained silicon layer A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that... |
| US-7,772,633 |
DRAM cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain... |
| US-7,772,632 |
Memory arrays and methods of fabricating memory arrays A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect... |
| US-7,772,583 |
Memory devices and methods of forming the same Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The... |
| US-7,772,537 |
Linear distributed pixel differential amplifier having mirrored inputs A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the... |
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