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| Patent # | Description |
|---|---|
| US-7,927,181 |
Apparatus for removing material from microfeature workpieces Machines and systems for removing materials from microfeature workpieces using fixed-abrasive mediums. One embodiment of a method for removing material from a... |
| US-7,925,949 |
Embedded processor Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a... |
| US-7,925,910 |
Systems, methods and devices for limiting current consumption upon
power-up Embodiments are described including those for controlling peak current consumption of a multi-chip memory package during power-up. In one embodiment, each... |
| US-7,925,844 |
Memory register encoding systems and methods Apparatus, systems, and methods are disclosed that operate to encode register bits to generate encoded bits such that, for pairs of addresses, an encoded bit to... |
| US-7,924,630 |
Techniques for simultaneously driving a plurality of source lines Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an... |
| US-7,924,623 |
Method for memory cell erasure with a programming monitor of reference
cells Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase... |
| US-7,924,619 |
Programming method to reduce word line to word line breakdown for NAND
flash A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of... |
| US-7,924,617 |
Selective threshold voltage verification and compaction Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of... |
| US-7,924,616 |
Word line voltage boost system and method for non-volatile memory devices
and memory devices and... The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by... |
| US-7,924,603 |
Resistance variable memory with temperature tolerant materials A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb.sub.2Se.sub.3, and... |
| US-7,924,337 |
Dual panel pixel readout in an imager An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual... |
| US-7,924,038 |
Probe and electrical connecting apparatus using it A probe having an alignment mark that is hardly influenced by scraps of an electrode scraped by a probe tip is provided. A probe according to the present... |
| US-7,924,034 |
Electric connecting apparatus In an electrical connecting apparatus, a thermal deformation restriction member, a reinforcing plate, and an auxiliary member are made of materials having... |
| US-7,923,824 |
Microelectronic component assemblies and microelectronic component lead
frame structures The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead... |
| US-7,923,381 |
Methods of forming electronic devices containing Zr-Sn-Ti-O films A dielectric film containing Zr--Sn--Ti--O and methods of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide... |
| US-7,923,373 |
Pitch multiplication using self-assembling materials Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed... |
| US-7,923,364 |
Tunnel dielectric comprising nitrogen for use with a semiconductor device
and a process for forming the device A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS... |
| US-7,923,322 |
Method of forming a capacitor A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed... |
| US-7,923,308 |
Methods of forming conductive contacts to source/drain regions and methods
of forming local interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local... |
| US-7,923,298 |
Imager die package and methods of packaging an imager die on a temporary
carrier Methods for fabricating an imager die package and resulting die packages are disclosed. An imager die packaging process may include dicing through a fabrication... |
| US-7,923,182 |
Multi-focus method of enhanced three-dimensional exposure of resist The field of this disclosure is making three-dimensional topographic structures by means of graduated exposure in a photosensitive material, such as a... |
| US-7,923,181 |
Methods of forming photomasks Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to... |
| US-7,923,070 |
Atomic layer deposition method of forming conductive metal
nitride-comprising layers This invention includes atomic layer deposition methods of forming conductive metal nitride comprising layers. In one implementation, an atomic layer deposition... |
| US-7,922,818 |
Method and system for binding halide-based contaminants A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized... |
| US-7,922,562 |
Systems and methods for reducing electrostatic charge of semiconductor
wafers A chemical-mechanical polishing machine and associated methods are disclosed. One embodiment of the machine includes a polishing pad, a wafer carrier... |
| US-7,920,431 |
Asynchronous/synchronous interface The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling... |
| US-7,920,428 |
Methods and apparatuses relating to automatic cell threshold voltage
measurement Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current... |
| US-7,920,427 |
Dynamic soft program trims Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming... |
| US-7,920,185 |
Shielding black reference pixels in image sensors An image sensor having an array of pixel cells, each including a photo-conversion device. The array has first, second, and third groups of pixel cells. The... |
| US-7,919,999 |
Band-gap reference voltage detection circuit Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage... |
| US-7,919,863 |
Semiconductor constructions Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second... |
| US-7,919,846 |
Stacked semiconductor component having through wire interconnect A stacked semiconductor component includes a plurality of semiconductor substrates in a stacked array and a continuous wire extending through aligned vias on... |
| US-7,919,829 |
Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a... |
| US-7,919,800 |
Capacitor-less memory cells and cell arrays A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of... |
| US-7,919,386 |
Methods of forming pluralities of capacitors The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a... |
| US-7,919,218 |
Method for a multiple exposure beams lithography tool An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by... |
| US-7,918,383 |
Methods for placing substrates in contact with molten solder Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder... |
| US-7,917,962 |
BIOS lock encode/decode driver Systems and methods for preventing the unauthorized access to data stored on removable media, such as software, include storing a predetermined signature in the... |
| US-7,917,685 |
Method for reading a multilevel cell in a non-volatile memory device A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell... |
| US-7,917,684 |
Bus translator Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus... |
| US-7,917,479 |
Non-volatile memory devices, systems including same and associated methods A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array... |
| US-7,916,557 |
NAND interface A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a... |
| US-7,916,553 |
Memory system and method having volatile and non-volatile memory devices
at same hierarchical level A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer... |
| US-7,916,546 |
Methods for programming a memory device and memory devices using inhibit
voltages that are less than a supply... Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less... |
| US-7,916,544 |
Random telegraph signal noise reduction scheme for semiconductor memories Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal... |
| US-7,916,543 |
Memory cell operation Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of... |
| US-7,916,536 |
Programming based on controller performance requirements Methods and solid state drives are disclosed, including a solid state drive that is adapted to receive and transmit analog data signals representative of bit... |
| US-7,916,396 |
Lens master devices, lens structures, imaging devices, and methods and
apparatuses of making the same A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a... |
| US-7,916,204 |
Multiple microlens system for image sensors or display An imager or display system with multiple lenses, which are formed, patterned and shaped over one or more pixels in an imager or display array. The multiple... |
| US-7,916,186 |
Anti-eclipse circuitry with tracking of floating diffusion reset level An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent... |
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