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| Patent # | Description |
|---|---|
| US-7,630,256 |
Erase operation in a flash drive memory A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the... |
| US-7,630,246 |
Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates... |
| US-7,630,241 |
Single latch data circuit in a multiple level call non-volatile memory
device A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a... |
| US-7,630,240 |
Read method for MLC Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data... |
| US-7,630,236 |
Flash memory programming to reduce program disturb The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to... |
| US-7,630,024 |
Assemblies and methods for illuminating a display A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing.... |
| US-7,630,008 |
Method of controlling image quality of an integrated CMOS imager and
microcontroller A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate... |
| US-7,629,858 |
Time delay oscillator for integrated circuits One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line... |
| US-7,629,819 |
Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the... |
| US-7,629,807 |
Electrical test probe A probe for electrical test comprises a plate-shaped main portion having a base end to be attached to a support board and a tip end opposite the base end, and a... |
| US-7,629,736 |
Method and device for preventing junction leakage in field emission
devices An apparatus and method for stabilizing a threshold voltage in an active matrix field emission device are disclosed. The method includes formation of... |
| US-7,629,693 |
Method for integrated circuit fabrication using pitch multiplication Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed... |
| US-7,629,686 |
Bumped die and wire bonded board-on-chip package An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a... |
| US-7,629,641 |
Band engineered nano-crystal non-volatile memory device utilizing enhanced
gate injection Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal... |
| US-7,629,630 |
Electropolished patterned metal layer for semiconductor devices An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or... |
| US-7,629,266 |
Etch compositions and methods of processing a substrate The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH.sub.4F and tetramethyl ammonium fluoride (TMAF). The... |
| US-7,629,250 |
Method for creating electrically conductive elements for semiconductor
device structures using laser ablation... A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon,... |
| US-7,629,249 |
Microfeature workpieces having conductive interconnect structures formed
by chemically reactive processes, and... Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance... |
| US-7,629,024 |
Methods of forming particle-containing materials The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials.... |
| US-7,628,932 |
Wet etch suitable for creating square cuts in si A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a... |
| US-7,628,855 |
Atomic layer deposition using electron bombardment Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor. |
| US-7,628,680 |
Method and apparatus for removing material from microfeature workpieces Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having... |
| US-7,627,796 |
Testing method for permanent electrical removal of an integrated circuit
output An apparatus and method of disconnecting or disabling an input/output terminal of an integrated circuit after packaging. Each input/output terminal of the... |
| US-7,627,793 |
Method and apparatus for generating and detecting initialization patterns
for high speed DRAM systems A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal... |
| US-7,627,772 |
Fast data access mode in a memory device A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A... |
| US-7,627,737 |
Processing element and method connecting registers to processing logic in
a plurality of configurations A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each... |
| US-7,627,568 |
Method and system for updating a search engine database based on
popularity of links A method and a system for maintaining the freshness of a search engine server's database. A popularity parameter is defined, and a popularity value is assigned... |
| US-7,626,877 |
Low voltage sense amplifier and sensing method Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the... |
| US-7,626,866 |
NAND flash memory programming A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the... |
| US-7,626,865 |
Charge pump operation in a non-volatile memory device A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial... |
| US-7,626,626 |
Method and apparatus providing pixel storage gate charge sensing for
electronic stabilization in imagers An imaging device that stores charge from a photosensor under at least one storage gate. A driver used to operate the at least one storage gate, senses how much... |
| US-7,626,416 |
Method and apparatus for high resolution ZQ calibration A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is... |
| US-7,626,269 |
Semiconductor constructions and assemblies, and electronic systems The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically... |
| US-7,626,252 |
Multi-chip electronic package and cooling system A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed... |
| US-7,626,238 |
Semiconductor devices having antireflective material In one aspect, the invention includes a semiconductor processing method. An antireflective material layer is formed over a substrate. At least a portion of the... |
| US-7,626,223 |
Memory structure for reduced floating body effect Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off... |
| US-7,626,219 |
Surround gate access transistors with grown ultra-thin bodies A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid... |
| US-7,625,803 |
Memory devices, electronic systems, and methods of forming memory devices The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is... |
| US-7,625,795 |
Container capacitor structure and method of formation thereof Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode ("bottom... |
| US-7,625,794 |
Methods of forming zirconium aluminum oxide A dielectric layer having atomic layer deposited zirconium aluminum oxide and a method of fabricating such a dielectric layer may produce a reliable dielectric... |
| US-7,625,776 |
Methods of fabricating intermediate semiconductor structures by
selectively etching pockets of implanted silicon A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one... |
| US-7,625,766 |
Methods of forming carbon nanotubes and methods of fabricating integrated
circuitry A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown... |
| US-7,625,694 |
Selective provision of a diblock copolymer material Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an... |
| US-7,625,641 |
Method of forming a crystalline phase material A method of forming a crystalline phase material includes: providing stress inducing material within or operatively adjacent a material of a first crystalline... |
| US-7,625,495 |
Methods and apparatuses for monitoring and controlling mechanical or
chemical-mechanical planarization of... Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate... |
| US-7,625,460 |
Multifrequency plasma reactor A multifrequency plasma reactor includes first, second and third power generators operably coupled to at least one of an upper and lower electrode for generating... |
| US-7,625,219 |
Electrical connecting apparatus The electrical connecting apparatus disclosed herein includes a frame member having a recess for receiving a device under test provided with a plurality of... |
| US-7,624,310 |
System and method for initializing a memory system, and memory device and
processor-based system using same Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory... |
| US-7,624,211 |
Method for bus width negotiation of data storage devices There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad... |
| US-7,624,180 |
Mixed enclave operation in a computer network A method is disclosed for mixed enclave operation of a computer network with users employing a multi-level network security interface and users without any... |
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