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| Patent # | Description |
|---|---|
| US-7,741,660 |
Pixel and imager device having high-k dielectrics in isolation structures An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention... |
| US-7,741,589 |
Method and apparatus providing multiple transfer gate control lines per
pixel for automatic exposure control An imager device includes a pixel array having some pixels providing output signals for automatic light control with other pixels providing image output signals.... |
| US-7,741,175 |
Methods of forming capacitors A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the... |
| US-7,741,150 |
Packaged microelectronic devices and methods for manufacturing packaged
microelectronic devices Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing... |
| US-7,739,576 |
Variable strength ECC Memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory controllers, memory systems, and/or... |
| US-7,738,988 |
Process and method for continuous, non lot-based integrated circuit
manufacturing A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes:... |
| US-7,738,310 |
Fuse data acquisition One or more embodiments of the present disclosure provide methods, devices, and systems for operating memory devices having fuse circuits. One method embodiment... |
| US-7,738,295 |
Programming a non-volatile memory device A non-volatile memory device that has a cache register coupled between each pair of bit lines and, in one embodiment, a data cache coupled between each pair of... |
| US-7,738,294 |
Programming multilevel cell memory arrays Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one... |
| US-7,738,292 |
Flash memory with multi-bit read A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory... |
| US-7,738,291 |
Memory page boosting method, device and system A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes... |
| US-7,737,741 |
Periodic signal delay apparatus, systems, and methods Apparatus, systems, and methods are disclosed that operate to delay a periodic input signal in one or more delay elements of a group of delay elements to... |
| US-7,737,729 |
Input buffer with optimal biasing and method thereof A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving... |
| US-7,737,559 |
Semiconductor constructions The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating... |
| US-7,737,536 |
Capacitive techniques to reduce noise in high speed interconnections Structures, in various embodiments, are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits.... |
| US-7,737,394 |
Ambient infrared detection in solid state sensors A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter... |
| US-7,737,055 |
Systems and methods for manipulating liquid films on semiconductor
substrates A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a... |
| US-7,737,047 |
Semiconductor constructions, and methods of forming dielectric materials Some embodiments include methods of forming dielectric materials associated with semiconductor constructions. A semiconductor substrate surface having two... |
| US-7,737,039 |
Spacer process for on pitch contacts and related structures Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated... |
| US-7,737,024 |
Small grain size, conformal aluminum interconnects and method for their
formation A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first... |
| US-7,737,022 |
Contact formation The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator... |
| US-7,737,010 |
Method of photoresist strip for plasma doping process of semiconductor
manufacturing A method of forming an intermediate semiconductor device is disclosed that comprises providing a semiconductor substrate, forming a photoresist layer on the... |
| US-7,736,987 |
Methods of forming semiconductor constructions The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention... |
| US-7,736,980 |
Vertical gated access transistor According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow... |
| US-7,736,969 |
DRAM layout with vertical FETS and method of formation DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The... |
| US-7,736,690 |
Method for manufacturing an electrical test probe A probe tip section of an electrical test probe has a laminated structure consisting of a first deposition portion and a second deposition portion covering the... |
| US-7,735,221 |
Method for manufacturing a multilayer wiring board A method of manufacturing a multilayer wiring board is provided. A flat surface is formed on a surface of a multilayer wiring layer, and resistive material is... |
| US-7,734,899 |
Reducing data hazards in pipelined processors to provide high processor
utilization A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of... |
| US-7,734,891 |
Robust index storage for non-volatile memory A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile... |
| US-7,733,731 |
Control of inputs to a memory device A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the... |
| US-7,733,705 |
Reduction of punch-through disturb during programming of a memory device A punch-through disturb effect in a memory device can be reduced by biasing a selected word line at a program voltage to program a selected memory cell, biasing... |
| US-7,733,699 |
Mimicking program verify drain resistance in a memory device A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the... |
| US-7,733,557 |
Spatial light modulators with changeable phase masks for use in
holographic data storage A holographic data storage system that includes a write head that includes a pixellated spatial light modulator and a separate or integral phase mask that varies... |
| US-7,733,392 |
Method and apparatus for reducing effects of dark current and defective
pixels in an imaging device A method and apparatus for identifying and compensating for the effects of defective pixels in high resolution digital cameras having image processing apparatus.... |
| US-7,733,262 |
Quantizing circuits with variable reference signals Systems, methods, and devices are disclosed, such as an integrated semiconductor device that may include a data location coupled to an electrical conductor, a... |
| US-7,733,118 |
Devices and methods for driving a signal off an integrated circuit Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an... |
| US-7,732,882 |
Method and system for electrically coupling a chip to chip package A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and... |
| US-7,732,852 |
High-K dielectric materials and processes for manufacturing them High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition... |
| US-7,732,533 |
Zwitterionic block copolymers and methods Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic... |
| US-7,732,343 |
Simplified pitch doubling process flow A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further... |
| US-7,732,247 |
Isolation techniques for reducing dark current in CMOS image sensors Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an... |
| US-7,732,221 |
Hybrid MRAM array structure and operation This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ... |
| US-7,730,372 |
Device and method for testing integrated circuit dice in an integrated
circuit module An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse... |
| US-7,729,197 |
Memory device having a delay locked loop with frequency control Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the... |
| US-7,729,191 |
Memory device command decoding system and memory device and
processor-based system using same Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to... |
| US-7,729,189 |
Switched capacitor DRAM sense amplifier with immunity to mismatch and
offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor... |
| US-7,729,182 |
Systems and methods for issuing address and data signals to a memory array Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked... |
| US-7,729,179 |
Random access memory employing read before write for resistance
stabilization An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase... |
| US-7,729,171 |
Multiple select gate architecture with select gates of different lengths The invention provides methods and apparatus. A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in... |
| US-7,729,167 |
Programming a memory with varying bits per cell Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates... |
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