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| Patent # | Description |
|---|---|
| US-7,638,813 |
Methods of fabrication for flip-chip image sensor packages The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the... |
| US-7,638,436 |
Semiconductor processing methods of transferring patterns from patterned
photoresists to materials The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first... |
| US-7,638,392 |
Methods of forming capacitor structures The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger... |
| US-7,638,357 |
Programmable resistance memory devices and systems using the same and
methods of forming the same A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first... |
| US-7,637,412 |
Apparatus and method for depositing and reflowing solder paste on a
microelectronic workpiece Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and... |
| US-7,636,271 |
User selectable banks for DRAM A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by... |
| US-7,635,991 |
Output buffer strength trimming Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage... |
| US-7,635,630 |
Scalable high density non-volatile memory cells in a contactless memory
array A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion... |
| US-7,635,623 |
Methods of forming capacitors A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising... |
| US-7,635,611 |
Semiconductor substrate for build-up packages The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach... |
| US-7,635,604 |
Well for CMOS imager and method of formation A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically... |
| US-7,635,132 |
Filter cloth connector Apparatuses and methods for making and using a filter cloth assembly are described. A filter cloth assembly can have a liquid permeable filtering medium attached... |
| US-7,635,079 |
System for locating conductive sphere utilizing screen and hopper of
solder balls System for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads.... |
| US-7,634,851 |
Method of forming a magnetic random access memory element A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a... |
| US-7,634,624 |
Memory system for data storage and retrieval According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system,... |
| US-7,634,623 |
Method and apparatus for self-timed data ordering for multi-data rate
memories and system incorporating same A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during... |
| US-7,634,597 |
Alignment of instructions and replies across multiple devices in a
cascaded system, using buffers of... Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the... |
| US-7,633,821 |
Current mode memory apparatus, systems, and methods Some embodiments include a first circuit to receive input signals and to drive signals at first circuit output nodes, and a second circuit to receive at least a... |
| US-7,633,804 |
Adjusting programming or erase voltage pulses in response to the number of
programming or erase failures Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to... |
| US-7,633,801 |
Memory in logic cell Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate,... |
| US-7,633,798 |
M+N bit programming and M+L bit read for M bit memory cells A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage... |
| US-7,633,786 |
Couplings within memory devices and methods Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer... |
| US-7,633,773 |
On-die anti-resonance structure for integrated circuit A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to... |
| US-7,633,423 |
Method of and apparatus for reducing settling time of a switched capacitor
amplifier A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an... |
| US-7,633,159 |
Semiconductor device assemblies and packages with edge contacts and
sacrificial substrates and other... A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which... |
| US-7,633,157 |
Microelectronic devices having a curved surface and methods for
manufacturing the same Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. In one embodiment, a device includes a support member and a... |
| US-7,633,116 |
One-transistor composite-gate memory One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect... |
| US-7,632,747 |
Conductive structures for microfeature devices and methods for fabricating
microfeature devices Methods for fabricating conductive structures on and/or in interposing devices and microfeature devices that are formed using such methods are disclosed herein.... |
| US-7,632,737 |
Protection in integrated circuits A method including, prior to a plasma heat-up operation, forming a liner on structure coated with an insulator. And a method including forming a trench on a... |
| US-7,632,702 |
Methods of forming a resistance variable element The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one... |
| US-7,631,170 |
Program controlled embedded-DRAM-DSP having improved instruction set
architecture An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register... |
| US-7,630,266 |
Temperature compensation of memory signals using digital signals A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates... |
| US-7,630,265 |
On-chip temperature sensor A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant... |
| US-7,630,256 |
Erase operation in a flash drive memory A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the... |
| US-7,630,246 |
Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates... |
| US-7,630,241 |
Single latch data circuit in a multiple level call non-volatile memory
device A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a... |
| US-7,630,240 |
Read method for MLC Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data... |
| US-7,630,236 |
Flash memory programming to reduce program disturb The method for reducing program disturb in a flash memory array biases a selected wordline at a programming voltage. One of the unselected wordlines, closer to... |
| US-7,630,024 |
Assemblies and methods for illuminating a display A computer display is disclosed. The computer display includes a LCD housing, a light source coupled to the LCD housing, and a LCD coupled to the LCD housing.... |
| US-7,630,008 |
Method of controlling image quality of an integrated CMOS imager and
microcontroller A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate... |
| US-7,629,858 |
Time delay oscillator for integrated circuits One aspect relates to an oscillator, and various oscillator embodiments comprise an amplifier and line driver with an input and an output and a transmission line... |
| US-7,629,819 |
Seamless coarse and fine delay structure for high performance DLL A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the... |
| US-7,629,807 |
Electrical test probe A probe for electrical test comprises a plate-shaped main portion having a base end to be attached to a support board and a tip end opposite the base end, and a... |
| US-7,629,736 |
Method and device for preventing junction leakage in field emission
devices An apparatus and method for stabilizing a threshold voltage in an active matrix field emission device are disclosed. The method includes formation of... |
| US-7,629,693 |
Method for integrated circuit fabrication using pitch multiplication Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed... |
| US-7,629,686 |
Bumped die and wire bonded board-on-chip package An apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a... |
| US-7,629,641 |
Band engineered nano-crystal non-volatile memory device utilizing enhanced
gate injection Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal... |
| US-7,629,630 |
Electropolished patterned metal layer for semiconductor devices An electropolishing process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or... |
| US-7,629,266 |
Etch compositions and methods of processing a substrate The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH.sub.4F and tetramethyl ammonium fluoride (TMAF). The... |
| US-7,629,250 |
Method for creating electrically conductive elements for semiconductor
device structures using laser ablation... A method for forming at least one conductive element is disclosed. Particularly, a semiconductor substrate, including a plurality of semiconductor dice thereon,... |
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