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Patent # Description
US-7,622,990 Amplifiers, methods of increasing current gain in amplifiers, and imaging devices
An amplifier includes a differential stage including a differential pair of transistors of a first conductivity type, the differential pair having gates, first...
US-7,622,986 High performance input receiver circuit for reduced-swing inputs
An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain "buffered"...
US-7,622,970 Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency
A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows...
US-7,622,969 Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock
Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal...
US-7,622,957 Pseudo-differential output driver with high immunity to noise and jitter
Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of...
US-7,622,908 Built-in system and method for testing integrated circuit timing parameters
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus...
US-7,622,798 Integrated circuit devices with stacked package interposers
An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a...
US-7,622,772 Electronic apparatuses, silicon-on-insulator integrated circuits, and fabrication methods
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate....
US-7,622,769 Isolation trench
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,622,388 Methods of forming titanium-containing materials
The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of...
US-7,622,377 Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment...
US-7,622,365 Wafer processing including dicing
Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a...
US-7,622,355 Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a...
US-7,622,321 High dielectric constant spacer for imagers
An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and...
US-7,622,049 Passivation for cleaning a material
A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove...
US-RE40,995 Multi-element resistive memory
A memory device.Iadd., and methods relating thereto, .Iaddend.having memory cells in which .[.a single.]. .Iadd.an .Iaddend.access transistor controls the...
US-7,620,859 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-7,620,789 Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate...
US-7,620,788 Memory device sequencer and method supporting multiple memory device clock speeds
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a...
US-7,620,768 Multiple erase block tagging in a flash memory device
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block...
US-7,619,933 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative...
US-7,619,931 Program-verify method with different read and verify pass-through voltages
Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array...
US-7,619,670 Rolling shutter for prevention of blooming
A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling...
US-7,619,669 Power savings with multiple readout circuits
An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within...
US-7,619,624 Methods and apparatus for rendering or preparing digital objects or portions thereof for subsequent processing
Methods and apparatus for rendering images of digital objects or for preparing digital objects for subsequent processing. The method includes sorting data...
US-7,619,458 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a...
US-7,619,453 Delay-locked loop (DLL) system for determining forward clock path delay
A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line...
US-7,619,449 Method and apparatus for synchronous clock distribution to a plurality of destinations
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a...
US-7,619,425 Electrical connecting apparatus
An electrical connecting apparatus comprises a plurality of plate-shaped probes. Each probe has a cut-off portion opening on its inside surface side and both...
US-7,619,404 System and method for testing integrated circuit timing margins
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,619,313 Multi-chip module and methods
A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at...
US-7,619,279 Three dimensional flash cell
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to...
US-7,619,247 Structure for amorphous carbon based non-volatile memory
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a...
US-7,619,184 Multi-parameter process and control method
A method and system for generating control settings for a multi-parameter control system. The interdependencies of processing tools and the related effect on...
US-7,618,901 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N.sub.2O and O.sub.3
This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous...
US-7,618,890 Methods for forming conductive structures and structures regarding same
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g. ruthenium oxide regions, at grain boundaries of a metal layer,...
US-7,618,874 Methods of forming capacitors
A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across...
US-7,618,751 RET for optical maskless lithography
The present invention relates to Optical Maskless Lithography (OML). In particular, it relates to providing OML with a recognizable relationship to mask and...
US-7,618,528 Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive...
Methods and apparatuses for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate. An apparatus...
US-7,617,355 Parity-scanning and refresh in dynamic memory devices
A method and apparatus that coordinates refresh and parity-scanning in DRAM-based devices such that parity-scan operations substitute for refresh operations when...
US-7,616,504 High speed array pipeline architecture
A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into...
US-7,616,489 Memory array segmentation and methods
The invention provides methods and apparatus. A memory array has a first well region having a first conductivity type. A plurality of second well regions of a...
US-7,616,482 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell includes two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,616,474 Offset compensated sensing for magnetic random access memory
An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the...
US-7,616,245 Active pixel sensor with a diagonal active area
An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent...
US-7,616,242 Linear-logarithmic pixel sensors and gain control circuits therefor
A system and method are disclosed to enlarge the sub-threshold current coefficient ".alpha." of a reset transistor connected to a photodiode in an L-L (Linear...
US-7,616,133 Data bus inversion apparatus, systems, and methods
Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of...
US-7,615,871 Method and apparatus for attaching microelectronic substrates and support members
A microelectronic package and method for forming such packages. In one embodiment, the package can be formed by providing a support member having a first...
US-7,615,438 Lanthanide yttrium aluminum oxide dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a...
US-7,615,164 Plasma etching methods and contact opening forming methods
The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma...
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