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Patent # Description
US-7,626,219 Surround gate access transistors with grown ultra-thin bodies
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid...
US-7,625,803 Memory devices, electronic systems, and methods of forming memory devices
The invention includes a memory device having a capacitor in combination with a transistor. The memory device can be within a TFT construction. The capacitor is...
US-7,625,795 Container capacitor structure and method of formation thereof
Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode ("bottom...
US-7,625,794 Methods of forming zirconium aluminum oxide
A dielectric layer having atomic layer deposited zirconium aluminum oxide and a method of fabricating such a dielectric layer may produce a reliable dielectric...
US-7,625,776 Methods of fabricating intermediate semiconductor structures by selectively etching pockets of implanted silicon
A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one...
US-7,625,766 Methods of forming carbon nanotubes and methods of fabricating integrated circuitry
A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown...
US-7,625,694 Selective provision of a diblock copolymer material
Disclosed herein are techniques for using diblock copolymer (DBCP) films as etch masks to form small dots or holes in integrated circuit layers. In an...
US-7,625,641 Method of forming a crystalline phase material
A method of forming a crystalline phase material includes: providing stress inducing material within or operatively adjacent a material of a first crystalline...
US-7,625,495 Methods and apparatuses for monitoring and controlling mechanical or chemical-mechanical planarization of...
Methods and devices for mechanical and/or chemical-mechanical planarization of semiconductor wafers, field emission displays and other microelectronic substrate...
US-7,625,460 Multifrequency plasma reactor
A multifrequency plasma reactor includes first, second and third power generators operably coupled to at least one of an upper and lower electrode for generating...
US-7,625,219 Electrical connecting apparatus
The electrical connecting apparatus disclosed herein includes a frame member having a recess for receiving a device under test provided with a plurality of...
US-7,624,310 System and method for initializing a memory system, and memory device and processor-based system using same
Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory...
US-7,624,211 Method for bus width negotiation of data storage devices
There is provided a method and apparatus for bus width negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad...
US-7,624,180 Mixed enclave operation in a computer network
A method is disclosed for mixed enclave operation of a computer network with users employing a multi-level network security interface and users without any...
US-7,623,568 System and method for testing a modem
A modem tester includes a signal reporting circuit which can report signals received from the modem of the computer. To test the operation of the modem in the...
US-7,623,392 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,623,365 Memory device interface methods, apparatus, and systems
Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on...
US-7,622,990 Amplifiers, methods of increasing current gain in amplifiers, and imaging devices
An amplifier includes a differential stage including a differential pair of transistors of a first conductivity type, the differential pair having gates, first...
US-7,622,986 High performance input receiver circuit for reduced-swing inputs
An input buffer receiver circuit for electronic devices (e.g., memory chips) to receive and process reduced-swing and high bandwidth inputs to obtain "buffered"...
US-7,622,970 Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency
A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows...
US-7,622,969 Methods, devices, and systems for a delay locked loop having a frequency divided feedback clock
Methods, devices, and systems are disclosed for a delay locked loop. A delay locked loop may comprise a delay line configured to receive a reference clock signal...
US-7,622,957 Pseudo-differential output driver with high immunity to noise and jitter
Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of...
US-7,622,908 Built-in system and method for testing integrated circuit timing parameters
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus...
US-7,622,798 Integrated circuit devices with stacked package interposers
An IC device includes a die and a first package interposer stacked over a second package interposer. The IC device includes a first conductive connection from a...
US-7,622,772 Electronic apparatuses, silicon-on-insulator integrated circuits, and fabrication methods
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate....
US-7,622,769 Isolation trench
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,622,388 Methods of forming titanium-containing materials
The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of...
US-7,622,377 Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment...
US-7,622,365 Wafer processing including dicing
Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a...
US-7,622,355 Write once read only memory employing charge trapping in insulators
Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a...
US-7,622,321 High dielectric constant spacer for imagers
An imager having gates with spacers formed of a high dielectric material. The high dielectric spacer provides larger fringing fields for charge transfer and...
US-7,622,049 Passivation for cleaning a material
A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove...
US-RE40,995 Multi-element resistive memory
A memory device.Iadd., and methods relating thereto, .Iaddend.having memory cells in which .[.a single.]. .Iadd.an .Iaddend.access transistor controls the...
US-7,620,859 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-7,620,789 Out of order DRAM sequencer
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate...
US-7,620,788 Memory device sequencer and method supporting multiple memory device clock speeds
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a...
US-7,620,768 Multiple erase block tagging in a flash memory device
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block...
US-7,619,933 Reducing effects of program disturb in a memory device
The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative...
US-7,619,931 Program-verify method with different read and verify pass-through voltages
Methods and devices are disclosed, such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array...
US-7,619,670 Rolling shutter for prevention of blooming
A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling...
US-7,619,669 Power savings with multiple readout circuits
An imager with a switch circuit located between, and connected to, the pixel array and associated readout chains. In one embodiment the switch is located within...
US-7,619,624 Methods and apparatus for rendering or preparing digital objects or portions thereof for subsequent processing
Methods and apparatus for rendering images of digital objects or for preparing digital objects for subsequent processing. The method includes sorting data...
US-7,619,458 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a...
US-7,619,453 Delay-locked loop (DLL) system for determining forward clock path delay
A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line...
US-7,619,449 Method and apparatus for synchronous clock distribution to a plurality of destinations
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a...
US-7,619,425 Electrical connecting apparatus
An electrical connecting apparatus comprises a plurality of plate-shaped probes. Each probe has a cut-off portion opening on its inside surface side and both...
US-7,619,404 System and method for testing integrated circuit timing margins
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,619,313 Multi-chip module and methods
A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at...
US-7,619,279 Three dimensional flash cell
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to...
US-7,619,247 Structure for amorphous carbon based non-volatile memory
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a...
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