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Patent # Description
US-7,615,164 Plasma etching methods and contact opening forming methods
The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma...
US-7,615,119 Apparatus for spin coating semiconductor substrates
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming...
US-7,614,149 Methods for assembling computers
Apparatuses and methods for preventing disengagement of electrical connectors in the assembly of computers. In one embodiment, a computer system includes a...
US-7,614,027 Methods for forming a MRAM with non-orthogonal wiring
The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed...
US-7,613,928 Flash device security method utilizing a check register
A security method for preventing accidental or unauthorized writes to a flash memory. According to one embodiment of the present invention, a BIOS program stored...
US-7,613,070 Interleaved input signal path for multiplexed input
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment,...
US-7,613,060 Methods, circuits, and systems to select memory regions
Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array...
US-7,613,031 System, apparatus, and method to increase read and write stability of scaled SRAM memory cells
Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by...
US-7,613,026 Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier...
US-7,613,025 Dram cell design with folded digitline architecture and angled active areas
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a...
US-7,613,024 Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells
A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively...
US-7,612,816 Low power comparator
A comparator with an input stage that selectively powers up an output stage provides an electronic device with a comparator that operates at low power. In an...
US-7,612,620 System and method for conditioning differential clock signals and integrated circuit load board using same
A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock...
US-7,612,574 Systems and methods for defect testing of externally accessible integrated circuit interconnects
Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads...
US-7,612,436 Packaged microelectronic devices with a lead frame
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged...
US-7,612,403 Low power non-volatile memory and gate stack
Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and...
US-7,612,393 Active photosensitive structure with buried depletion layer
An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a...
US-7,611,980 Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n.gtoreq.2, tiers of stacked mandrels are...
US-7,611,971 Method of removing residual contaminants from an environment
A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the...
US-7,611,959 Zr-Sn-Ti-O films
A dielectric layer containing a Zr--Sn--Ti--O film and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent...
US-7,611,944 Integrated circuit fabrication
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a...
US-7,611,809 Multi-layer, attenuated phase-shifting mask
The present invention provides an attenuated phase shift mask ("APSM") that, in each embodiment, includes completely transmissive regions sized and shaped to...
US-7,610,525 Defective memory block identification in a memory device
During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the...
US-7,610,524 Memory with test mode output
Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command...
US-7,610,503 Methods for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,610,502 Computer systems having apparatus for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,610,430 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,609,583 Selective edge phase mixing
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and...
US-7,609,565 External clock tracking pipelined latch scheme
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data...
US-7,609,563 Simultaneous read circuit for multiple memory cells
A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit....
US-7,609,560 Sensing of memory cells in a solid state memory device by fixed discharge of a bit line
In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to...
US-7,609,559 Word line drivers having a low pass filter circuit in non-volatile memory device
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line...
US-7,609,557 Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
US-7,609,554 High voltage switching circuit
A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and, an enhancement mode NMOS transistor. A...
US-7,609,549 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,609,302 Correction of non-uniform sensitivity in an image array
An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries...
US-7,608,927 Localized biasing for silicon on insulator structures
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned...
US-7,608,904 Semiconductor device components with conductive vias and systems including the components
A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a...
US-7,608,876 Merged MOS-bipolar capacitor memory cell
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source...
US-7,608,788 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,608,495 Transistor forming methods
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and...
US-7,608,196 Method of forming high aspect ratio apertures
A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment...
US-7,608,195 High aspect ratio contacts
A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty...
US-7,607,177 Secure compact flash
An embodiment of the present invention includes a nonvolatile memory card including a controller and nonvolatile memory coupled to the controller, the controller...
US-7,606,448 Zinc oxide diodes for optical interconnections
The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined...
US-7,606,102 Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using...
US-7,606,101 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory...
US-7,606,097 Array sense amplifiers, memory devices and systems including same, and methods of operation
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output ("I/O") node and a second...
US-7,606,088 Sense amplifier circuit
The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated...
US-7,606,075 Read operation for NAND memory
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated...
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