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Patent # Description
US-7,595,844 Method for assisting video compression in a computer system
One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task...
US-7,595,521 Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
US-7,594,322 Methods of fabricating substrates including at least one conductive via
A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate,...
US-7,594,257 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be...
US-7,594,088 System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device...
US-7,593,287 READ command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,593,286 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,593,272 Detection of row-to-row shorts and other row decode defects in memory devices
A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage...
US-7,593,254 Variable resistance memory device with an interfacial adhesion heating layer, systems using the same and...
A variable resistance memory element and method of forming the same. The memory element includes a first electrode, a resistivity interfacial layer having a...
US-7,592,691 High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies
A stacked semiconductor die assembly includes at least two partially offset semiconductor dice with bond pads located adjacent at least one peripheral side...
US-7,592,251 Hafnium tantalum titanium oxide films
Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in...
US-7,592,246 Method and semiconductor device having copper interconnect for bonding
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,592,242 Apparatus and method for controlling diffusion
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,592,218 Methods of forming vertical transistors
A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess...
US-7,592,212 Methods for determining a dose of an impurity implanted in a semiconductor substrate
Methods of determining a total impurity dose for a plasma doping process, and an apparatus configured to determine same. A total ion dose implanted in a...
US-7,592,107 Polarized reticle, photolithography system, and method of fabricating a polarized reticle
Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed...
US-7,592,105 Methods for converting reticle configurations and methods for modifying reticles
The invention includes methods of converting reticles from configurations suitable for utilization with later generation (shorter wavelength) stepper radiations...
US-7,591,959 Etchants and etchant systems with plural etch selectivities
An etchant for removing materials with a plurality of selectivities exhibits a first etch selectivity at a first temperature and a second etch selectivity at a...
US-7,591,069 Methods of bonding solder balls to bond pads on a substrate, and bonding frames
Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame...
US-7,591,061 Method for securing a subpad to a subpad support
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad...
US-7,590,966 Data path for high performance pattern generator
A method and system for a high-speed datapath for a high-performance pattern generator such as an analog SLM for generating the image is disclosed. The data path...
US-7,590,797 System and method for optimizing interconnections of components in a multichip memory module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have...
US-7,590,764 System and method for dynamic buffer allocation
A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to...
US-7,590,019 Low voltage data path and current sense amplifier
Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output...
US-7,589,995 One-transistor memory cell with bias gate
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate....
US-7,589,573 Startup circuit and method
A startup circuit provides a single connection to a node of a reference or other circuit to be started. The startup circuit injects high current into devices to...
US-7,589,426 Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and...
US-7,589,406 Stacked semiconductor component
A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive...
US-7,589,369 Semiconductor constructions
The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array...
US-7,589,029 Atomic layer deposition and conversion
A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the...
US-7,589,015 Fabrication of semiconductor devices using anti-reflective coatings
Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface...
US-7,589,010 Semiconductor devices with permanent polymer stencil and method for manufacturing the same
Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces...
US-7,589,008 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the...
US-7,588,988 Method of forming apparatus having oxide films formed using atomic layer deposition
A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a...
US-7,588,982 Methods of forming semiconductor constructions and flash memory cells
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
US-7,588,870 Dual layer workpiece masking and manufacturing process
The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described...
US-7,588,804 Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
Reactors having isolated gas connectors, systems that include such reactors, and methods for depositing materials onto micro-devices workpieces are disclosed...
US-7,588,677 Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a...
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, the method can include engaging a microelectronic...
US-7,587,560 Memory device controller
A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core...
US-7,586,799 Devices, systems, and methods for independent output drive strengths
Methods, apparatuses and systems are disclosed for independently configurable data and strobe drivers within a memory device. A memory device may include at...
US-7,586,784 Apparatus and methods for programming multilevel-cell NAND memory devices
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first...
US-7,586,777 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,586,329 Capacitively-coupled level restore circuits for low voltage swing logic circuits
Some embodiments of the disclosure include a circuit having differential sides and a capacitive network coupled to differential sides. The circuit further...
US-7,586,321 Electrical test probe and electrical test probe assembly
An electrical test probe comprises a probe tip portion and a probe main body portion having a pedestal portion on which the probe tip portion is formed to be...
US-7,586,319 Methods of retaining semiconductor component configurations within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,586,316 Probe board mounting apparatus
A mounting apparatus that does not compromise the strength of a probe board. The apparatus comprises a probe board spaced from a support member by a spacer. A...
US-7,586,144 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,585,782 Methods of forming semiconductor constructions, and methods of selectively removing metal-containing materials...
The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing...
US-7,585,753 Controlling diffusion in doped semiconductor regions
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,585,741 Methods of forming capacitors
The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the...
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