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Patent # Description
US-7,660,144 High-performance one-transistor memory cell
A memory cell embodiment includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential...
US-7,659,727 Multilayer wiring board and method for testing the same
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of...
US-7,659,630 Interconnect structures with interlayer dielectric
The present invention relates to metallic interconnect having an interlayer dielectric thereover, the metallic interconnect having an upper surface substantially...
US-7,659,612 Semiconductor components having encapsulated through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact....
US-7,659,560 Transistor structures
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill...
US-7,659,211 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect....
US-7,659,210 Nano-crystal etch process
A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing...
US-7,659,208 Method for forming high density patterns
Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. In one or more embodiments, a method is...
US-7,659,205 Amorphous carbon-based non-volatile memory
A resistance variable memory element and a method for forming the same. The memory element has an amorphous carbon layer between first and second electrodes. A...
US-7,659,181 Sub-micron space liner and filler process
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an...
US-7,659,161 Methods of forming storage nodes for a DRAM array
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,659,152 Localized biasing for silicon on insulator structures
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned...
US-7,659,151 Flip chip with interposer, and methods of making same
A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller...
US-7,657,813 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured....
US-7,657,802 Data compression read mode for memory testing
A first series combination of bit match circuits compares a predetermined bit position in data words that are involved in a compression operation. The first...
US-7,657,723 System and method for processor with predictive memory retrieval assist
A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the...
US-7,656,961 Method and apparatus for multi-user transmission
A method of transmitting data signals from at least two transmitting terminals to at least one receiving terminal with a spatial diversity antenna comprises...
US-7,656,768 Phase masks for use in holographic data storage
A spatial light modulator (SLM) having a phase mask that is provided as an internal component thereof. The phase mask can be provided as a multilevel surface of...
US-7,656,745 Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes...
US-7,656,740 Wordline voltage transfer apparatus, systems, and methods
The apparatus and systems comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a...
US-7,656,720 Power-off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
US-7,656,709 NAND step up voltage switching method
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a...
US-7,656,209 Output slew rate control
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver...
US-7,656,166 Multilayer wiring board and method for testing the same
A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which...
US-7,656,049 CMOS device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-7,656,012 Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices...
A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The...
US-7,656,006 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse transistor...
US-7,655,973 Recessed channel negative differential resistance-based memory cell
Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of...
US-7,655,968 Semiconductor devices
A method for forming double-sided capacitors for a semiconductor device includes forming a dielectric structure which supports capacitor bottom plates during...
US-7,655,508 Overmolding encapsulation process and encapsulated article made therefrom
A method of encapsulating an article having first and second surfaces, includes positioning the article on a carrier such that at least a portion of the first...
US-7,655,507 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,655,500 Packaged microelectronic devices and methods for packaging microelectronic devices
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
US-7,655,387 Method to align mask patterns
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming...
US-7,655,384 Methods for reducing spherical aberration effects in photolithography
Methods to at least partially compensate for photoresist-induced spherical aberration that occurs during mask imaging used for photolithographic processing of...
US-7,655,095 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
US-7,652,703 Dual panel pixel readout in an imager
An imager having two panels of pixels (i.e., the imager's rows of pixels are split into two panels) that are controllable by separate row decoders. The dual...
US-7,652,669 Animation packager for an on-line book
A system for creating an on-line book with an animated cover. The system includes an animation program for inserting an animation sequence at the beginning of an...
US-7,652,495 Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using...
Pusher assemblies for use in microelectronic device testing systems and methods for using such pusher assemblies are disclosed herein. One particular embodiment...
US-7,652,365 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,651,956 Process for fabricating films of uniform properties on semiconductor devices
A process for forming a thin layer exhibiting a substantially uniform property on an active surface of a semiconductor substrate. The process includes varying...
US-7,651,951 Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns....
US-7,651,911 Memory transistor and methods
A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At...
US-7,651,910 Methods of forming programmable memory devices
The invention includes a method of forming a programmable memory device. A tunnel oxide is formed to be supported by a semiconductor substrate. A stack is formed...
US-7,650,588 Methods and systems for pattern generation based on multiple forms of design data
In a pattern generation method, properties of designs are extracted in a mask data preparation system, and the properties are propagated to a lithography write...
US-7,650,541 Memory block quality identification in a memory device
If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect....
US-7,649,783 Delayed activation of selected wordlines in memory
Apparatus, systems, and methods may operate to receive an external read command at a control circuit coupled to a memory array. Individual wordline activation...
US-7,649,316 Assemblies for plasma-enhanced treatment of substrates
Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of...
US-7,649,201 Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels
An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised...
US-7,649,145 Compliant spring contact structures
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a...
US-7,648,926 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
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