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Patent # Description
US-7,609,563 Simultaneous read circuit for multiple memory cells
A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit....
US-7,609,560 Sensing of memory cells in a solid state memory device by fixed discharge of a bit line
In one or more of the disclosed embodiments, a memory device is provided that reads a target memory cell by first charging the series string of memory cells to...
US-7,609,559 Word line drivers having a low pass filter circuit in non-volatile memory device
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line...
US-7,609,557 Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
US-7,609,554 High voltage switching circuit
A high voltage switching circuit that has a depletion mode NMOS transistor, an enhancement mode PMOS transistor and, an enhancement mode NMOS transistor. A...
US-7,609,549 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,609,302 Correction of non-uniform sensitivity in an image array
An improved non-uniform sensitivity correction algorithm for use in an imager device (e.g., a CMOS APS). The algorithm provides zones having flexible boundaries...
US-7,608,927 Localized biasing for silicon on insulator structures
A silicon-on-insulator device has a localized biasing structure formed in the insulator layer of the SOI. The localized biasing structure includes a patterned...
US-7,608,904 Semiconductor device components with conductive vias and systems including the components
A semiconductor device component includes at least one conductive via. The at least one conductive via may include a seed layer for facilitating adhesion of a...
US-7,608,876 Merged MOS-bipolar capacitor memory cell
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source...
US-7,608,788 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,608,495 Transistor forming methods
A transistor forming method includes forming a dielectric spacer in a trench surrounding an active area island, forming line openings through the spacer, and...
US-7,608,196 Method of forming high aspect ratio apertures
A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment...
US-7,608,195 High aspect ratio contacts
A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty...
US-7,607,177 Secure compact flash
An embodiment of the present invention includes a nonvolatile memory card including a controller and nonvolatile memory coupled to the controller, the controller...
US-7,606,448 Zinc oxide diodes for optical interconnections
The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined...
US-7,606,102 Memory address repair without enable fuses
A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using...
US-7,606,101 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory...
US-7,606,097 Array sense amplifiers, memory devices and systems including same, and methods of operation
A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output ("I/O") node and a second...
US-7,606,088 Sense amplifier circuit
The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated...
US-7,606,075 Read operation for NAND memory
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated...
US-7,606,055 Memory architecture and cell design employing two access transistors
An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access...
US-7,605,934 Method and system for facsimile delivery using dial-up modem pools
A method and system for communicating a facsimile (fax) message over a computer network. A user initiates the sending of the fax to a recipient fax transceiver...
US-7,605,852 Real-time exposure control for automatic light control
An imager and a method for real-time, non-destructive monitoring of light incident on imager pixels during their exposure to light. Real-time or present pixel...
US-7,605,650 Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy
A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is...
US-7,605,631 Delay line synchronizer apparatus and method
A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock...
US-7,605,620 System and method to improve the efficiency of synchronous mirror delays and delay locked loops
A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore...
US-7,605,611 Methods, devices, and systems for a high voltage tolerant buffer
Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric...
US-7,605,417 Assemblies comprising magnetic elements and magnetic barrier or shielding at least partially around the...
The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First...
US-7,605,350 System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing
In general, the system provides for soft baking a semiconductor wafer so that photoresist layers on the wafer are free of surface voids or craters. In...
US-7,605,034 Integrated circuit memory cells and methods of forming
An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor...
US-7,605,033 Low resistance peripheral local interconnect contacts with selective wet strip of titanium
Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that...
US-7,605,030 Hafnium tantalum oxynitride high-k dielectric and metal gates
Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum...
US-7,605,028 Method of forming a memory device having a storage transistor
A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion...
US-7,604,729 Methods and apparatus for selectively removing conductive material from a microelectronic substrate
Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the...
US-7,604,527 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a...
US-7,603,772 Methods of fabricating substrates including one or more conductive vias
Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of...
US-7,603,534 Synchronous flash memory with status burst output
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in...
US-7,603,493 Dynamically setting burst length of memory device by applying signal to at least one external pin during a read...
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
US-7,602,876 Method and apparatus for generating a phase dependent control signal
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector...
US-7,602,630 Configurable inputs and outputs for memory stacking system and method
Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of...
US-7,602,618 Methods and apparatuses for transferring heat from stacked microfeature devices
Apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support...
US-7,602,200 Probe for electrical test comprising a positioning mark and probe assembly
A probe for electrical test provided with positioning marks parallel to a plane where tips are provided and at a height position lower than the plane on a plane...
US-7,602,049 Capacitive techniques to reduce noise in high speed interconnections
Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits....
US-7,602,039 Programmable capacitor associated with an input/output pad
The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus...
US-7,602,030 Hafnium tantalum oxide dielectrics
A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety...
US-7,602,009 Erasable non-volatile memory device using hole trapping in high-K dielectrics
A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control...
US-7,602,001 Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one...
This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An...
US-7,601,649 Zirconium-doped tantalum oxide films
A dielectric film containing zirconium-doped tantalum oxide arranged as a structure of one or more monolayers and a method of fabricating such a dielectric film...
US-7,601,608 Memory array buried digit line
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a...
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