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Power saving sensing scheme for solid state memory
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a...
Method and system for selectively limiting peak power consumption during
programming or erase of non-volatile...
A power supply circuit is used to supply power having a limited peak magnitude to an array of non-volatile memory cells during programming or erasing of the...
Method and system for minimizing number of programming pulses used to
program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
Method and system for programming non-volatile memory cells based on
programming of proximate memory cells
A multi-level non-volatile memory device programs cells in each row in a manner that takes into account the coupling from the programming of cells that are...
Hidden hinge MEMS device
The present invention relates to a method for manufacturing a MEMS device, including the actions of: providing a substrate having a back and front surface...
Method for isolating a short-circuited integrated circuit (IC) from other
ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are...
Thin film transistors and semiconductor constructions
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
DRAM including a vertical surround gate transistor
DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect...
Method of making a one transistor SOI non-volatile random access memory
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
SOI device with reduced drain induced barrier lowering
A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing...
Methods and systems for removing materials from microfeature workpieces
with organic and/or non-aqueous...
Methods and systems for removing materials from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes...
Method and system for transferring data to an electronic toy or other
A method for transferring data from a display device to an electronic device includes displaying a visual pattern on the display device. The visual pattern...
Background block erase check for flash memories
Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations...
Resistive heater for thermo optic device
Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing...
Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
Memory system and method having volatile and non-volatile memory devices
at same hierarchical level
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer...
Method and apparatus for improving storage performance using a background
Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of...
High slew rate amplifier, analog-to-digital converter using same, CMOS
imager using the analog-to-digital...
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one...
Power on reset circuitry in electronic systems
One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment...
High-density single transistor vertical memory gain cell
A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate....
Merged MOS-bipolar capacitor memory cell
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source...
Gettering using voids formed by surface transformation
One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The...
Hafnium lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of...
Critical dimension control for integrated circuits
Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma...
Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
Semiconductor structures including vertical diode structures and methods
of making the same
Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode...
Reduced barrier photodiode / gate device structure for high efficiency
charge transfer and reduced lag and...
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the...
Apparatus for conditioning chemical-mechanical polishing pads
An apparatus for conditioning a polishing pad, or conditioner, includes a supporting substrate and abrasive elements. The abrasive elements of the conditioner...
Method and apparatus for testing a memory device with compressed data
using a single output
A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data...
Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
Method for using data regarding manufacturing procedures integrated
circuits (ICS) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether...
Data strobe synchronization circuit and method for double data rate,
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control...
NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
Programming method to reduce word line to word line breakdown for NAND
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of...
Non-volatile memory copy back
Data move operations in a memory device are included that enable identification of data errors. During a write operation, identified errors are flagged and used...
Absolute value peak differential voltage detector circuit and method
A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector...
Method and apparatus for selecting an operating mode based on a
determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
Small grain size, conformal aluminum interconnects and method for their
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
Device structures including ruthenium silicide diffusion barrier layers
A device structure including a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion...
Spacer patterned, high dielectric constant capacitor
A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A...
Atomic layer deposition and conversion
A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the...
Non-volatile memory cell device and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the...
Enhanced memory density resistance variable memory cells, arrays, devices
and systems including the same, and...
A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable...
Atomic layer deposited hafnium tantalum oxide dielectrics
A dielectric layer containing hafnium tantalum film arranged as a structure of one or more monolayers and a method of fabricating such a dielectric layer produce...
Systems and methods of forming refractory metal nitride layers using
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
Electrical components for microelectronic devices and methods of forming
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing...
Multiple spacer steps for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed...
Methods for selectively filling apertures in a substrate to form
conductive vias with a liquid using a vacuum
Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing...
DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...