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Patent # Description
US-1,008,4114 Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
US-1,008,4084 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-1,008,4016 Cross-point memory and methods for fabrication of same
A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The...
US-1,008,3984 Integrated structures and methods of forming integrated structures
Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A...
US-1,008,3981 Memory arrays, and methods of forming memory arrays
Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends...
US-1,008,3973 Apparatuses and methods for reading memory cells
Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line...
US-1,008,3941 Stacked semiconductor dies with selective capillary under fill
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a...
US-1,008,3937 Semiconductor devices and packages and methods of forming semiconductor device packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
US-1,008,3931 Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes...
US-1,008,3751 Data state synchronization
The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a...
US-1,008,3745 Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric...
US-1,008,3744 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-1,008,3734 Memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,008,3733 Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a...
US-1,008,3732 Memory cell imprint avoidance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a...
US-1,008,3731 Memory cell sensing with storage component isolation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection...
US-1,008,3727 Apparatuses and methods for concurrently accessing different memory planes of a memory
Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a...
US-1,008,3725 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-1,008,3723 Apparatuses and methods for sharing transmission vias for memory devices
Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies,...
US-1,008,3265 Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing...
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the...
US-1,008,3122 Transactional memory
Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
US-1,008,3119 Memory having a static cache and a dynamic cache
The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first...
US-1,008,3078 Method and apparatus for a volume management system in a non-volatile memory device
Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks...
US-1,008,2976 Method and apparatus for configuring write performance for electrically writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration...
US-1,008,2975 Obfuscation-enhanced memory encryption
The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation,...
US-1,008,2964 Data caching for ferroelectric memory
Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row...
US-1,007,9340 Phase change memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements....
US-1,007,9333 Solid-state radiation transducer devices having flip-chip mounted solid-state radiation transducers and...
Solid-state radiation transducer (SSRT) devices and methods of manufacturing and using SSRT devices are disclosed herein. One embodiment of the SSRT device...
US-1,007,9246 Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
US-1,007,9244 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed....
US-1,007,9235 Memory cells and memory arrays
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to...
US-1,007,9169 Backside stealth dicing through tape followed by front side laser ablation dicing process
A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on...
US-1,007,9065 Reduced voltage nonvolatile flash memory
Systems include a first semiconductor die comprising a charge pump to generate power supply signals, a second semiconductor die comprising a memory array and...
US-1,007,9064 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory...
US-1,007,9063 Apparatuses and methods for charging a global access line prior to accessing a memory
Apparatuses and methods for charging a global access line prior to accessing a memory are described. An example apparatus may include a memory array of a...
US-1,007,9050 Apparatuses and methods for providing an indicator of operational readiness of various circuits of a...
Apparatuses and methods for providing an indicator of operational readiness of various circuits of a semiconductor device following power up are described in...
US-1,007,9049 Stack access control for memory device
Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die....
US-1,007,8546 Temperature related error management
Apparatuses and methods for temperature related error management are described. One or more apparatuses for temperature related error management can include an...
US-1,007,8449 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A...
US-1,007,5392 Methods and apparatuses for processing multiple communications signals with a single integrated circuit chip
An apparatus is disclosed. The apparatus comprises a plurality of antennas and an integrated circuit chip coupled to the plurality of antennas, and is...
US-1,007,4724 Apparatus including gettering agents in memory charge storage structures
Apparatus having a processor and a memory device in communication with the processor, the memory device including an array of memory cells and a control logic...
US-1,007,4693 Connections for memory electrode lines
Subject matter disclosed herein relates to an integrated circuit device having a socket interconnect region for connecting a plurality of conductive lines at a...
US-1,007,4662 Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and...
US-1,007,4633 Semiconductor die assemblies having molded underfill structures and related technology
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate...
US-1,007,4603 Methods of forming a semiconductor device comprising first and second nitride layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
US-1,007,4599 Semiconductor dies with recesses, associated leadframes, and associated systems and methods
Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one...
US-1,007,4443 Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input...
US-1,007,4442 Semiconductor device and control method of the same
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of...
US-1,007,4432 Programming of memory devices
Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage,...
US-1,007,4431 3D NAND memory Z-decoder
Apparatus and methods are disclosed, including an apparatus having first and second units of vertically arranged strings of memory cells, each unit including...
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