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Patent # Description
US-7,553,472 Nanotube forming methods
A nanotube forming method includes growing a plurality of nanotubes to an intermediate length that is deterministic of nanotube intrinsic conductivity....
US-7,552,364 Diagnostic and managing distributed processor system
A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a...
US-7,552,274 Flash memory architecture with separate storage of overhead and user data
A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The...
US-7,551,748 Earphone
The receiver unit includes a receiver body, a housing containing this receiver body, a cord connected to the receiver body, and a cord protector for protecting...
US-7,551,510 Memory block reallocation in a flash memory device
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability....
US-7,551,509 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary...
US-7,551,481 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,551,467 Memory device architectures and operation
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines...
US-7,551,466 Bit line coupling
The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed...
US-7,550,985 Methods of testing memory devices
A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least...
US-7,550,848 Semiconductor constructions comprising particle-containing materials
The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials....
US-7,550,847 Packaged microelectronic devices and methods for packaging microelectronic devices
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
US-7,550,824 Low k interconnect dielectric using surface transformation
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit...
US-7,550,818 Method of manufacture of a PCRAM memory cell
The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having...
US-7,550,816 Filled trench isolation structure
A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing...
US-7,550,762 Isolation circuit
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a...
US-7,550,380 Electroless plating of metal caps for chalcogenide-based memory devices
A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first...
US-7,550,345 Methods of forming hafnium-containing materials
The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is...
US-7,550,341 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column....
US-7,550,340 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
US-7,550,339 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,550,315 Method for fabricating semiconductor package with multi-layer die contact and external contact
A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package...
US-RE40,790 Method for making electrical contact with an active area through sub-micron contact openings and a...
A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive...
US-7,549,143 Method and device for checking lithography data
Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features...
US-7,549,142 Method and device for checking lithography data
Devices and methods are provided that include advantages such as the ability to identify sizes, shapes and locations of frequently unwanted additional features...
US-7,549,033 Dual edge command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-7,549,011 Bit inversion in memory devices
Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the...
US-7,548,667 Optical integrated circuit
The present technique relates to a device including an optical integrated circuit amplifier and another type of optical integrated circuit. The optical...
US-7,548,483 Memory device and method having multiple address, data and command buses
A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address...
US-7,548,459 Method, apparatus, and system providing adjustable memory page configuration
A method, apparatus and system providing a memory device having an array of cells which may be selectively designated for either error correction code use or...
US-7,547,978 Underfill and encapsulation of semiconductor assemblies with materials having differing properties
Polymerized materials for forming the underfill and encapsulation structures for semiconductor package are disclosed. A filler constituent, such as boron...
US-7,547,954 Electronic systems using optical waveguide interconnects formed through a semiconductor wafer
An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor...
US-7,547,949 Semiconductor structures and memory device constructions
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,547,945 Transistor devices, transistor structures and semiconductor constructions
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-7,547,935 Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device...
A method of electrically linking contacts of a semiconductor device to their corresponding digit lines. The method includes disposing a quantity of mask material...
US-7,547,905 Programmable conductor memory cell structure and method therefor
In programmable conductor memory cells, metal ions precipitate out of a glass electrolyte element in response to an applied electric field in one direction only,...
US-7,547,877 Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers
Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including...
US-7,547,850 Semiconductor device assemblies with compliant spring contact structures
Photolithography patterned spring contacts are disclosed. The spring contacts may be fabricated using thin film processing techniques. A substrate, such as a...
US-7,547,640 Method for integrated circuit fabrication using pitch multiplication
Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed...
US-7,547,617 Semiconductor device including container having epitaxial silicon therein
Methods for growing epitaxial silicon are provided. Methods for controlling bottom stacking fault propagation in epitaxial silicon are also provided.
US-7,547,604 Method of forming a recessed gate structure on a substrate having insulating columns and removing said...
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,547,599 Multi-state memory cell
Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate...
US-7,547,579 Underfill process
A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically...
US-7,547,559 Method for forming MRAM bit having a bottom sense layer utilizing electroless plating
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a...
US-7,547,213 Memory modules and methods for manufacturing memory modules
Memory modules and methods for manufacturing memory modules are disclosed herein. In one embodiment, a memory module includes a substrate, a microelectronic...
US-7,546,435 Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
US-7,546,416 Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring...
US-7,545,682 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,545,674 Flash memory with low tunnel barrier interpoly insulators
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region...
US-7,545,669 Resistive memory device
A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal,...
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