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Patent # Description
US-7,564,733 Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
US-7,564,731 Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
US-7,564,722 Memory system and method having volatile and non-volatile memory devices at same hierarchical level
A processor-based system includes a processor coupled to core logic through a processor bus. This includes a dynamic random access memory ("DRAM") memory buffer...
US-7,564,721 Method and apparatus for improving storage performance using a background erase
Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of...
US-7,564,397 High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital...
An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one...
US-7,564,279 Power on reset circuitry in electronic systems
One or more embodiments of the present disclosure provide methods, devices, and systems for operating power on reset (POR) circuitry. One method embodiment...
US-7,564,088 High-density single transistor vertical memory gain cell
A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate....
US-7,564,087 Merged MOS-bipolar capacitor memory cell
A high density vertical merged MOS-bipolar-capacitor gain cell is realized for DRAM operation. The gain cell includes a vertical MOS transistor having a source...
US-7,564,082 Gettering using voids formed by surface transformation
One aspect of this disclosure relates to a semiconductor structure, comprising a gettering region proximate to a device region in a semiconductor wafer. The...
US-7,563,730 Hafnium lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of...
US-7,563,723 Critical dimension control for integrated circuits
Methods of etching substrates with small critical dimensions and altering the critical dimensions are disclosed. In one embodiment, a sulfur oxide based plasma...
US-7,563,679 Reduction of field edge thinning in peripheral devices
A dielectric layer (e.g., an interpoly dielectric layer) is deposited over low and high voltage devices of a peripheral memory device. The dielectric behaves as...
US-7,563,666 Semiconductor structures including vertical diode structures and methods of making the same
Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode...
US-7,563,631 Reduced barrier photodiode / gate device structure for high efficiency charge transfer and reduced lag and...
A pixel cell having a reduced potential barrier near a region where a gate and a photodiode are in close proximity to one another, and a method for forming the...
US-7,563,157 Apparatus for conditioning chemical-mechanical polishing pads
An apparatus for conditioning a polishing pad, or conditioner, includes a supporting substrate and abrasive elements. The abrasive elements of the conditioner...
US-7,562,268 Method and apparatus for testing a memory device with compressed data using a single output
A method and apparatus for testing a memory device with compressed data using multiple clock edges is disclosed. In one embodiment of the present invention data...
US-7,562,178 Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,561,938 Method for using data regarding manufacturing procedures integrated circuits (ICS) have undergone, such as...
An inventive method in an integrated circuit (IC) manufacturing process for using data regarding repair procedures conducted on ICs at probe to determine whether...
US-7,561,477 Data strobe synchronization circuit and method for double data rate, multi-bit writes
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control...
US-7,561,472 NAND architecture memory with voltage sensing
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or...
US-7,561,469 Programming method to reduce word line to word line breakdown for NAND flash
A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of...
US-7,561,466 Non-volatile memory copy back
Data move operations in a memory device are included that enable identification of data errors. During a write operation, identified errors are flagged and used...
US-7,560,959 Absolute value peak differential voltage detector circuit and method
A peak voltage detector is used to detect the absolute value of the peak differential amplitude of a differential input signal. The peak voltage detector...
US-7,560,956 Method and apparatus for selecting an operating mode based on a determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
US-7,560,816 Small grain size, conformal aluminum interconnects and method for their formation
A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first...
US-7,560,815 Device structures including ruthenium silicide diffusion barrier layers
A device structure including a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion...
US-7,560,799 Spacer patterned, high dielectric constant capacitor
A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A...
US-7,560,793 Atomic layer deposition and conversion
A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the...
US-7,560,769 Non-volatile memory cell device and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the...
US-7,560,723 Enhanced memory density resistance variable memory cells, arrays, devices and systems including the same, and...
A resistance variable memory cell and method of forming the same. The memory cell includes a first electrode and at least one layer of resistance variable...
US-7,560,395 Atomic layer deposited hafnium tantalum oxide dielectrics
A dielectric layer containing hafnium tantalum film arranged as a structure of one or more monolayers and a method of fabricating such a dielectric layer produce...
US-7,560,393 Systems and methods of forming refractory metal nitride layers using disilazanes
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum (silicon) nitride barrier...
US-7,560,392 Electrical components for microelectronic devices and methods of forming the same
Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing...
US-7,560,390 Multiple spacer steps for pitch multiplication
Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed...
US-7,560,371 Methods for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum
Methods of forming a conductive via in a substrate include contacting the substrate with a wave of conductive liquid material, such as molten solder, and drawing...
US-7,560,336 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,560,335 Memory device transistors
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
US-7,560,305 Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures...
US-7,560,017 Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or...
Methods and apparatuses for detecting characteristics of a microelectronic substrate. A method in accordance with an embodiment of the invention includes...
US-7,559,773 Electrical connecting apparatus
The present invention prevents damage of adjacent mounting portions caused by heat at the time of mounting of contactors and further reduces the arrangement...
US-RE40,842 Memory elements and methods for making same
Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and...
US-7,558,142 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,558,133 System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
US-7,558,131 NAND system with a data write frequency greater than a command-and-address-load frequency
The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second...
US-7,558,130 Adjustable drive strength apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die...
US-7,558,125 Input buffer and method with AC positive feedback, and a memory device and computer system using same
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative...
US-7,558,102 Device and method having a memory array storing each bit in multiple memory cells
A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store "1" and "0"...
US-7,557,631 Voltage and temperature compensation delay system and method
A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input...
US-7,557,628 Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N...
US-7,557,620 System and method for controlling input buffer biasing current
A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a...
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