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Patent # Description
US-7,589,369 Semiconductor constructions
The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array...
US-7,589,029 Atomic layer deposition and conversion
A method for growing films for use in integrated circuits using atomic layer deposition and a subsequent converting step is described. In an embodiment, the...
US-7,589,015 Fabrication of semiconductor devices using anti-reflective coatings
Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface...
US-7,589,010 Semiconductor devices with permanent polymer stencil and method for manufacturing the same
Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces...
US-7,589,008 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces having such interconnects are disclosed herein. One aspect of the...
US-7,588,988 Method of forming apparatus having oxide films formed using atomic layer deposition
A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a...
US-7,588,982 Methods of forming semiconductor constructions and flash memory cells
Some embodiments include methods of forming flash memory cells and semiconductor constructions, and some embodiments include semiconductor constructions. Some...
US-7,588,870 Dual layer workpiece masking and manufacturing process
The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described...
US-7,588,804 Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
Reactors having isolated gas connectors, systems that include such reactors, and methods for depositing materials onto micro-devices workpieces are disclosed...
US-7,588,677 Methods and apparatus for electrical, mechanical and/or chemical removal of conductive material from a...
A method and apparatus for removing conductive material from a microelectronic substrate. In one embodiment, the method can include engaging a microelectronic...
US-7,587,560 Memory device controller
A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core...
US-7,586,799 Devices, systems, and methods for independent output drive strengths
Methods, apparatuses and systems are disclosed for independently configurable data and strobe drivers within a memory device. A memory device may include at...
US-7,586,784 Apparatus and methods for programming multilevel-cell NAND memory devices
Methods and apparatus are provided. A first data value is read from a first memory cell and is stored. An attempt is made to add a second data value to the first...
US-7,586,777 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,586,329 Capacitively-coupled level restore circuits for low voltage swing logic circuits
Some embodiments of the disclosure include a circuit having differential sides and a capacitive network coupled to differential sides. The circuit further...
US-7,586,321 Electrical test probe and electrical test probe assembly
An electrical test probe comprises a probe tip portion and a probe main body portion having a pedestal portion on which the probe tip portion is formed to be...
US-7,586,319 Methods of retaining semiconductor component configurations within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,586,316 Probe board mounting apparatus
A mounting apparatus that does not compromise the strength of a probe board. The apparatus comprises a probe board spaced from a support member by a spacer. A...
US-7,586,144 Memory device with high dielectric constant gate dielectrics and metal floating gates
A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator...
US-7,585,782 Methods of forming semiconductor constructions, and methods of selectively removing metal-containing materials...
The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing...
US-7,585,753 Controlling diffusion in doped semiconductor regions
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,585,741 Methods of forming capacitors
The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the...
US-7,585,728 Methods of programming memory cells using manipulation of oxygen vacancies
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-7,585,725 Use of dilute steam ambient for improvement of flash devices
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an...
US-7,585,707 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-7,585,425 Apparatus and method for reducing removal forces for CMP pads
An improvement in a polishing apparatus for planarizing substrates comprises a tenacious coating of a low-adhesion material to the platen surface. An expendable...
US-7,585,371 Substrate susceptors for receiving semiconductor substrates to be deposited upon
In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the...
US-7,584,942 Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in...
Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in reaction chambers are disclosed herein. In one...
US-7,584,343 Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM...
US-7,583,551 Power management control and controlling memory refresh operations
A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring,...
US-7,583,534 Memory utilizing oxide-conductor nanolaminates
One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is...
US-7,583,358 Systems and methods for retrieving residual liquid during immersion lens photolithography
Systems and methods for retrieving residual liquid during immersion lens photolithography are disclosed. A method in accordance with one embodiment includes...
US-7,583,115 Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal...
US-7,583,070 Zero power start-up circuit for self-bias circuit
An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its...
US-7,582,570 Compositions for removal of processing byproducts and method for using same
A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The...
US-7,582,562 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-7,582,561 Method of selectively depositing materials on a substrate using a supercritical fluid
A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a...
US-7,582,549 Atomic layer deposited barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-7,582,180 Systems and methods for processing microfeature workpieces
Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece...
US-7,582,161 Atomic layer deposited titanium-doped indium oxide films
An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and...
US-7,581,511 Apparatus and methods for manufacturing microfeatures on workpieces using plasma vapor processes
A reactor comprising an energy source, a plasma unit positioned relative to the energy source, and a processing vessel connected to the plasma unit. The energy...
US-7,581,080 Method for manipulating data in a group of processing elements according to locally maintained counts
The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving...
US-7,581,055 Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly...
US-7,580,887 Method and apparatus for facilitating purchase transactions across a network
A local computer system that provides and records information to facilitate a purchase transaction across a network operates by first receiving a request for...
US-7,580,287 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-7,580,286 Selective threshold voltage verification and compaction
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of...
US-7,580,283 System and memory for sequential multi-plane page memory operations
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory...
US-7,580,279 Flash memory cells with reduced distances between cell elements
An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of...
US-7,579,862 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,579,684 Methods for packing microfeature devices and microfeature devices formed by such methods
Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods...
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