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Patent # Description
US-7,585,741 Methods of forming capacitors
The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the...
US-7,585,728 Methods of programming memory cells using manipulation of oxygen vacancies
One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect...
US-7,585,725 Use of dilute steam ambient for improvement of flash devices
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an...
US-7,585,707 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-7,585,425 Apparatus and method for reducing removal forces for CMP pads
An improvement in a polishing apparatus for planarizing substrates comprises a tenacious coating of a low-adhesion material to the platen surface. An expendable...
US-7,585,371 Substrate susceptors for receiving semiconductor substrates to be deposited upon
In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the...
US-7,584,942 Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in...
Ampoules for producing a reaction gas and systems for depositing materials onto microfeature workpieces in reaction chambers are disclosed herein. In one...
US-7,584,343 Data reordering processor and method for use in an active memory device
An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM...
US-7,583,551 Power management control and controlling memory refresh operations
A memory devices provide signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring,...
US-7,583,534 Memory utilizing oxide-conductor nanolaminates
One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is...
US-7,583,358 Systems and methods for retrieving residual liquid during immersion lens photolithography
Systems and methods for retrieving residual liquid during immersion lens photolithography are disclosed. A method in accordance with one embodiment includes...
US-7,583,115 Delay line off-state control with power reduction
A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal...
US-7,583,070 Zero power start-up circuit for self-bias circuit
An improved start-up circuit and method for self-bias circuits is described that applies a start-up voltage and current to a self-bias circuit to initialize its...
US-7,582,570 Compositions for removal of processing byproducts and method for using same
A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The...
US-7,582,562 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-7,582,561 Method of selectively depositing materials on a substrate using a supercritical fluid
A method for depositing one or more materials on a substrate, such as for example, a semiconductor substrate that includes providing the substrate; applying a...
US-7,582,549 Atomic layer deposited barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-7,582,180 Systems and methods for processing microfeature workpieces
Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece...
US-7,582,161 Atomic layer deposited titanium-doped indium oxide films
An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and...
US-7,581,511 Apparatus and methods for manufacturing microfeatures on workpieces using plasma vapor processes
A reactor comprising an energy source, a plasma unit positioned relative to the energy source, and a processing vessel connected to the plasma unit. The energy...
US-7,581,080 Method for manipulating data in a group of processing elements according to locally maintained counts
The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving...
US-7,581,055 Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly...
US-7,580,887 Method and apparatus for facilitating purchase transactions across a network
A local computer system that provides and records information to facilitate a purchase transaction across a network operates by first receiving a request for...
US-7,580,287 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-7,580,286 Selective threshold voltage verification and compaction
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of...
US-7,580,283 System and memory for sequential multi-plane page memory operations
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory...
US-7,580,279 Flash memory cells with reduced distances between cell elements
An anti-reflective coating (ARC) is formed over the various layers involved in a cell fabrication process. The ARC is selectively etched such that the edges of...
US-7,579,862 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,579,684 Methods for packing microfeature devices and microfeature devices formed by such methods
Methods for packaging microfeature devices on and/or in microfeature workpieces at the wafer level and microfeature devices that are formed using such methods...
US-7,579,681 Super high density module with integrated wafer level packages
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of...
US-7,579,615 Access transistor for memory device
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second...
US-7,579,278 Topography directed patterning
A pattern having exceptionally small features is formed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern comprises...
US-7,579,267 Methods and systems for fabricating semiconductor components with through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact....
US-7,579,242 High performance multi-level non-volatile memory device
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping...
US-7,579,240 Method of making vertical transistor with horizontal gate layers
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable...
US-7,579,235 Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode...
US-7,578,056 Method of coating contacts on a surface of a flip chip
A method for encapsulating a flip chip in one step is disclosed. The flip chip is immersed in a polymer bath to apply a coating of the polymer to the surface of...
US-D598,894 Earphone
US-7,577,830 Peripheral device with hardware linked list
A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers...
US-7,577,790 Caching of dynamic arrays
Systems and methods are provided for caching dynamic arrays. According to one aspect, a cache memory device is provided for caching dynamic arrays or dynamic...
US-7,577,212 Method and system for generating reference voltages for signal receivers
A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In...
US-7,577,044 Resistive memory element sensing using averaging
A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage...
US-7,577,036 Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of...
US-7,577,027 Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the...
US-7,576,441 Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device
A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials...
US-7,576,400 Circuitry and gate stacks
The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon,...
US-7,576,398 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,576,380 Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an...
US-7,576,378 Systems and methods for forming metal oxides using metal diketonates and/or ketoimines
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,576,012 Atomic layer deposition methods
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in...
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