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Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
Twin p-well CMOS imager
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in...
Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
Barrier layer, IC via, and IC line forming methods
A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and...
Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
Methods of forming semiconductor devices, assemblies and constructions
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another...
Method for fabricating board on chip (BOC) semiconductor package with
circuit side polymer layer
A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing...
ALD methods in which two or more different precursors are utilized with
one or more reactants to form materials...
In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M.sub.2-M.sub.1-R- and...
Embedded fiber acoustic sensor for CMP process endpoint
Devices, systems and methods for monitoring characteristics of semiconductor substrates and workpieces during planarization and for endpointing planarization...
Wide frequency range signal generator and method, and integrated circuit
test system using same
A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a...
Memory system with user configurable density/performance option
The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple...
DRAM cells and electronic systems
The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and...
SLM addressing methods and apparatuses
A spatial light modulator may include a plurality of deflectable modulating elements. Each of the deflectable modulating elements may further include a support...
Dynamic well bias controlled by Vt detector
The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the...
Reduced time constant charge pump and method for charging a capacitive
A charge pump and method converts an input voltage to a boosted voltage having a magnitude or polarity that is different from that of the input voltage. The...
Output impedance calibration circuit with multiple output driver models
A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area...
Semiconductor constructions comprising multi-level patterns of
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
Structures and methods to enhance copper metallization
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a...
Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
Semiconductor device containing an ultra thin dielectric film or
An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A...
Reduced imager crosstalk and pixel noise using extended buried contacts
Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer...
Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
Memory device fabrication
The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed...
Methods for assembly and packaging of flip chip configured dice with
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor...
Dicing saw blade positioning apparatus and methods independent of blade
thickness via constrained biasing elements
An apparatus for positioning dicing saw blades at a fixed axial distance from one another independent of the thicknesses of the saw blades, where the saw blade...
Multiple operating system quick boot utility
A computerized user interface for assisting a computer user selects a default operating system for a computer. The computerized interface operates during a...
Memory hub and method for memory system performance monitoring
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
System and method for hidden-refresh rate modification
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a...
Bitline exclusion in verification operation
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting...
Non-volatile one time programmable memory
A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further...
Phase interpolation apparatus, systems, and methods
A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal...
A probe assembly having a plurality of probes, each of which is secured to an anchor portion on a probe base plate, extends in a direction apart from the anchor...
Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. A semiconductor device assembly includes a conductively bumped...
Lanthanum aluminum oxynitride dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of...
Microelectronic devices and methods for forming interconnects in
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
Method and system for fabricating semiconductor components with through
interconnects and back side...
A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of...
Semiconductor capacitor structure and method to form same
A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride...
Methods of forming a layer comprising epitaxial silicon, and methods of
forming field effect transistors
Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising...
Method of forming CMOS imager with capacitor structures
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are...
Methods of forming a conductive interconnect in a pixel of an imager and
in other integrated circuitry
A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal...
Semiconductor processor systems, a system configured to provide a
semiconductor workpiece process fluid
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
Memory device internal parameter reliability
Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and...
Memory subsystem voltage control and method that reprograms a preferred
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
Memory modules having a memory hub containing a posted write buffer, a
memory device interface and a link...
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that...
Dynamic volume management for flash memories
A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a...
Zinc oxide optical waveguides
The present disclosure includes methods, devices, and systems having zinc oxide waveguides for optical signal interconnections. One optical signal interconnect...
Circuit and method for reducing noise interference in digital differential
A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an...
Method and system for synchronizing communications links in a hub-based
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs...
Single level cell programming in a multiple level cell non-volatile memory
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire...