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Patent # Description
US-7,547,640 Method for integrated circuit fabrication using pitch multiplication
Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed...
US-7,547,617 Semiconductor device including container having epitaxial silicon therein
Methods for growing epitaxial silicon are provided. Methods for controlling bottom stacking fault propagation in epitaxial silicon are also provided.
US-7,547,604 Method of forming a recessed gate structure on a substrate having insulating columns and removing said...
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,547,599 Multi-state memory cell
Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric layer and/or the intergate...
US-7,547,579 Underfill process
A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically...
US-7,547,559 Method for forming MRAM bit having a bottom sense layer utilizing electroless plating
The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a...
US-7,547,213 Memory modules and methods for manufacturing memory modules
Memory modules and methods for manufacturing memory modules are disclosed herein. In one embodiment, a memory module includes a substrate, a microelectronic...
US-7,546,435 Dynamic command and/or address mirroring system and method for memory modules
A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The...
US-7,546,416 Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring...
US-7,545,682 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,545,674 Flash memory with low tunnel barrier interpoly insulators
Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region...
US-7,545,669 Resistive memory device
A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal,...
US-7,545,388 Apparatus, method, and product for downscaling an image
An average filter or filters is used in line with the output of an interpolation filter to downscale an image. The interpolation filter upscales a source image...
US-7,545,183 Integrated circuit comparator or amplifier
An integrated circuit comparator comprises a differential amplifier, a source follower circuit coupled to a gate terminal of a first transistor in the...
US-7,545,009 Word lines for memory cells
Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material...
US-7,544,990 Scalable integrated logic and non-volatile memory
A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and...
US-7,544,989 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column....
US-7,544,987 High-k dielectric materials and processes for manufacturing them
High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition...
US-7,544,986 System including integrated circuit structures formed in a silicone ladder polymer layer
A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder...
US-7,544,984 Gettering using voids formed by surface transformation
One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and...
US-7,544,921 Linear distributed pixel differential amplifier having mirrored inputs
A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the...
US-7,544,624 Systems and methods for processing microfeature workpieces
Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece...
US-7,544,622 Passivation for cleaning a material
A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove...
US-7,544,615 Systems and methods of forming refractory metal nitride layers using organic amines
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on...
US-7,544,604 Tantalum lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of...
US-7,544,596 Atomic layer deposition of GdScO3 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd.sub.2O.sub.3) and scandium oxide (Sc.sub.2O.sub.3) acting as a...
US-7,544,592 Method for increasing etch rate during deep silicon dry etch
A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of...
US-7,544,584 Localized compressive strained semiconductor
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline...
US-7,544,563 Methods of forming a plurality of capacitors
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,544,559 Methods of forming semiconductor constructions
The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material...
US-7,544,554 Methods of forming gatelines and transistor devices
The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for...
US-7,544,506 System and method for heating, cooling and heat cycling on microfluidic device
An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and...
US-7,544,388 Methods of depositing materials over substrates, and methods of forming layers over substrates
The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is...
US-7,542,614 Image feature identification and motion compensation apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may estimate the magnitude of relative motion between a scene and an image capture device used to capture the...
US-7,542,336 Architecture and method for NAND flash memory
A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are...
US-7,542,319 Chalcogenide glass constant current device, and its method of fabrication and operation
The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a...
US-7,542,129 Patterning apparatuses and methods for the same
An apparatus for patterning a workpiece may include at least two spatial light modulators. The at least two spatial light modulators may receive and relay...
US-7,541,963 Variable quantization ADC for image sensors
An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system,...
US-7,541,871 Operational transconductance amplifier (OTA)
Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include...
US-7,541,851 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
US-7,541,825 Isolation circuit
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first...
US-7,541,658 Optically interactive device package array
An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls...
US-7,541,648 Electrostatic discharge (ESD) protection circuit
An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs)...
US-7,541,635 Semiconductor fabrication using a collar
In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first...
US-7,541,632 Relaxed-pitch method of aligning active area to digit line
According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at...
US-7,541,270 Methods for forming openings in doped silicon dioxide
Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma...
US-7,541,242 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,541,081 Phase change memory for archival data storage
A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a...
US-7,540,018 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be...
US-7,539,921 Parity bit system for a CAM
A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status...
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