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Patent # Description
US-7,713,885 Methods of etching oxide, reducing roughness, and forming capacitor constructions
The invention includes methods in which one or more components of a carboxylic acid having an aqueous acidic dissociation constant of at least 1.times.10.sup.-6...
US-7,713,857 Methods of forming an antifuse and a conductive interconnect, and methods of forming DRAM circuitry
A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through...
US-7,713,841 Methods for thinning semiconductor substrates that employ support structures formed on the substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor...
US-7,713,817 Methods of forming semiconductor structures
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be...
US-7,713,813 Methods of forming capacitors
The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a...
US-7,713,430 Using positive DC offset of bias RF to neutralize charge build-up of etch features
Apparatus, systems and methods for plasma etching substrates are provided. The invention achieves dissipation of charge build-up on a substrate being plasma...
US-7,712,211 Method for packaging circuits and packaged circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate...
US-7,710,805 Maintenance of amplified signals using high-voltage-threshold transistors
Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate...
US-7,710,786 NAND flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a...
US-7,710,765 Back gated SRAM cell
Methods, devices and systems for a back gated static random access memory (SRAM) cell are provided. One method embodiment for operating an SRAM cell includes...
US-7,710,760 Method and apparatus for charging large capacitances
A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator...
US-7,710,634 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,709,946 Micro universal serial bus (USB) memory package
A micro USB memory package and method for manufacturing the same, which can meet the USB standard specification, can have a light, thin, short and small...
US-7,709,885 Access transistor for memory device
An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second...
US-7,709,877 High surface area capacitor structures and precursors
A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low...
US-7,709,777 Pumps for CMOS imagers
A pixel for an imaging device is described. The pixel includes a photosensitive device provided within a substrate for providing photo-generated charges, a...
US-7,709,402 Conductive layers for hafnium silicon oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a HfSiON film on a substrate for use in a variety of electronic systems. The HfSiON...
US-7,709,399 Atomic layer deposition systems and methods including metal .beta.-diketiminate compounds
The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one .beta.-diketiminate ligand. Such...
US-7,709,390 Methods of isolating array features during pitch doubling processes and semiconductor device structures having...
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one...
US-7,709,345 Trench isolation implantation
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth...
US-7,709,343 Use of a plasma source to form a layer during the formation of a semiconductor device
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
US-7,709,341 Methods of shaping vertical single crystal silicon walls and resulting structures
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon...
US-7,709,327 Methods of forming semiconductor-on-insulator substrates, and integrated circuitry
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,709,326 Methods of forming layers comprising epitaxial silicon
The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over...
US-7,709,289 Memory elements having patterned electrodes and method of forming the same
A memory element having a resistance variable material and methods for forming the same are provided. The method includes forming a plurality of first electrodes...
US-7,709,279 Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events...
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD...
US-7,709,165 Image enhancement for multiple exposure beams
An aspect of the present invention includes a method for patterning a workpiece covered at least partly with a layer sensitive to electromagnetic radiation by...
US-7,708,875 Noncontact localized electrochemical deposition of metal thin films
A method of selectively depositing metal features on a conductive surface of a substrate. An electrode assembly that includes a plurality of electrodes connected...
US-7,708,622 Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces
Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for...
US-7,707,718 Methods for assembling computers
Apparatuses and methods for preventing disengagement of electrical connectors in the assembly of computers. In one embodiment, a computer system includes a...
US-7,707,473 Integrated testing apparatus, systems, and methods
Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test...
US-7,707,467 Input/output compression and pin reduction in an integrated circuit
An I/O compression apparatus, for testing a memory array and/or a logic circuit, is comprised of a selectable compression circuit that outputs compressed test...
US-7,707,368 Memory device trims
Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory...
US-7,706,647 Resistive heater for thermo optic device
Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing...
US-7,705,965 Backside lithography and backside immersion lithography
The present disclosure relates to formation of latent images in a radiation sensitive layer applied to a substrate that is transparent to or transmissive of...
US-7,705,963 Pupil improvement of incoherent imaging systems for enhanced CD linearity
A pattern generator may include an electromagnetic radiation source and an optical system. The electromagnetic radiation source may emit electromagnetic...
US-7,705,677 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,705,664 Current mirror circuit having drain-source voltage clamp
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output...
US-7,705,429 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,705,389 Thickened sidewall dielectric for memory cell
Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a...
US-7,705,383 Integrated circuitry for semiconductor memory
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor...
US-7,705,349 Test inserts and interconnects with electrostatic discharge structures
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD...
US-7,704,884 Semiconductor processing methods
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a...
US-7,704,849 Methods of forming trench isolation in silicon of a semiconductor substrate by plasma
A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask...
US-7,704,794 Method of forming a semiconductor device
A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than...
US-7,704,673 Prevention of photoresist scumming
A photo acid generator (PAG) or an acid is used to reduce resist scumming and footing. Diffusion of acid from photoresist into neighbors causes a decreased acid...
US-7,702,949 Use of non-volatile memory to perform rollback function
A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is...
US-7,701,788 Apparatus and method for selectively configuring a memory device using a bi-stable relay
The disclosed embodiments of the present invention include a semiconductor memory apparatus having a selectable memory capacity. In one embodiment, a system...
US-7,701,782 Signal transfer apparatus and methods
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of...
US-7,701,780 Non-volatile memory cell healing
Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first...
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