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Patent # Description
US-7,524,756 Process of forming a semiconductor assembly having a contact structure and contact liner
A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact...
US-7,524,410 Methods and apparatus for removing conductive material from a microelectronic substrate
A method and apparatus for removing conductive material from a microelectronic substrate is disclosed. One method includes disposing an electrolytic liquid...
US-7,523,539 Method of manufacturing a probe
In a probe manufacturing method, after a metal material for a probe is deposited on a base table, the probe can be detached from the base table relatively easily...
US-7,523,400 Text based markup language resource interface
A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference...
US-7,523,381 Non-volatile memory with error detection
Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated...
US-7,522,466 DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as...
US-7,522,341 Sharing of microlenses among pixels in image sensors
A microlens array having microlenses that correspond to more than one color filter and underlying pixel. In one particular embodiment, each microlens is formed...
US-7,521,967 Methods of reducing data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-7,521,956 Methods and apparatus for adaptively adjusting a data receiver
Methods are provided to reduce offsets and timing skews in data signals captured in a data receiver by adaptively adjusting a transition threshold of the data...
US-7,521,948 Integrated circuit load board and method having on-board test circuit
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,521,794 Intrinsic thermal enhancement for FBGA package
A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the...
US-7,521,705 Reproducible resistance variable insulating memory devices having a shaped bottom electrode
The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the...
US-7,521,378 Low temperature process for polysilazane oxidation/densification
Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed....
US-7,521,373 Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-7,521,371 Methods of forming semiconductor constructions having lines
In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically...
US-7,521,356 Atomic layer deposition systems and methods including silicon-containing tantalum precursor compounds
The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): ...
US-7,521,355 Integrated circuit insulators and related methods
A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for...
US-7,521,354 Low k interlevel dielectric layer fabrication methods
A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide...
US-7,521,322 Vertical transistors
Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to...
US-7,521,296 Methods of fabricating a microlens including selectively curing flowable, uncured optically trasmissive material
Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material....
US-7,519,882 Intelligent binning for electrically repairable semiconductor chips
The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests...
US-7,519,881 Device and method for testing integrated circuit dice in an integrated circuit module
An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse...
US-7,519,877 Memory with test mode output
Apparatus and methods of forming and operating the apparatus provide an instrumentality for a memory to generate a test mode signal to trigger a test in response...
US-7,519,850 Method and unit for buffer control
A system unit including a processor unit and an input storage unit. The processor unit generates an input signal and a clock signal. The input storage unit...
US-7,519,788 System and method for an asynchronous data buffer having buffer write and read pointers
A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device...
US-7,518,914 Non-volatile memory device with both single and multiple level cells
A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either...
US-7,518,422 Switched capacitor for a tunable delay circuit
A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a...
US-7,518,302 Method of fabricating field emission arrays employing a hard mask to define column lines and another mask to...
Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive...
US-7,518,246 Atomic layer deposition of CeO.sub.2/Al.sub.2O.sub.3 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer...
US-7,518,237 Microfeature systems including adhered microfeature workpieces and support members
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-7,518,227 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,518,223 Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least...
US-7,518,212 Graded Ge.sub.xSe.sub.100-x concentration in PCRAM
The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse...
US-7,518,184 DRAM access transistor
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,518,182 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,518,174 Memory cell and method for forming the same
A semiconductor memory cell structure having 4F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and...
US-7,517,804 Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide...
US-7,517,798 Methods for forming through-wafer interconnects and structures resulting therefrom
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
US-7,517,797 Carrier for wafer-scale package, wafer-scale package including the carrier, and methods
A carrier for use in a chip-scale package includes a semiconductor substrate with a plurality of apertures formed therethrough. The apertures of the carrier are...
US-7,517,786 Methods of forming wire bonds for semiconductor constructions
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
US-7,517,783 Molybdenum-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain...
US-7,517,758 Method of forming a vertical transistor
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,517,754 Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically...
US-7,517,753 Methods of forming pluralities of capacitors
The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically...
US-7,517,749 Method for forming an array with polysilicon local interconnects
Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature...
US-7,517,744 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,517,743 Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,517,704 MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the...
US-7,517,558 Methods for positioning carbon nanotubes
The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment,...
US-7,516,363 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
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