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Patent # Description
US-7,531,906 Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. A semiconductor device assembly includes a conductively bumped...
US-7,531,869 Lanthanum aluminum oxynitride dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of...
US-7,531,453 Microelectronic devices and methods for forming interconnects in microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
US-7,531,443 Method and system for fabricating semiconductor components with through interconnects and back side...
A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of...
US-7,531,421 Semiconductor capacitor structure and method to form same
A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride...
US-7,531,395 Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising...
US-7,531,379 Method of forming CMOS imager with capacitor structures
A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are...
US-7,531,373 Methods of forming a conductive interconnect in a pixel of an imager and in other integrated circuitry
A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal...
US-7,530,877 Semiconductor processor systems, a system configured to provide a semiconductor workpiece process fluid
Semiconductor processor systems, systems configured to provide a semiconductor workpiece process fluid, semiconductor workpiece processing methods, methods of...
US-7,529,969 Memory device internal parameter reliability
Embodiments herein may store redundant copies of an operational parameter associated with an internal operation of a memory device. The redundant copies and...
US-7,529,951 Memory subsystem voltage control and method that reprograms a preferred operating voltage
A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a...
US-7,529,896 Memory modules having a memory hub containing a posted write buffer, a memory device interface and a link...
A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that...
US-7,529,882 Dynamic volume management for flash memories
A method for managing a range of memory in a flash memory space in which a plurality of data objects are stored. A volume defined for the range of memory has a...
US-7,529,460 Zinc oxide optical waveguides
The present disclosure includes methods, devices, and systems having zinc oxide waveguides for optical signal interconnections. One optical signal interconnect...
US-7,529,318 Circuit and method for reducing noise interference in digital differential input receivers
A circuit and method reduces noise signals coupled to a reference voltage used by a digital differential input receiver having an input that is coupled to an...
US-7,529,273 Method and system for synchronizing communications links in a hub-based memory system
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs...
US-7,529,129 Single level cell programming in a multiple level cell non-volatile memory device
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire...
US-7,528,932 SLM direct writer
The present invention relates to an apparatus (100) for patterning a workpiece arranged at an image plane and sensitive to electromagnetic radiation, comprising...
US-7,528,877 Method and system for reducing mismatch between reference and intensity paths in analog to digital converters...
A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied...
US-7,528,638 Clock signal distribution with reduced parasitic loading effects
Clock signal distribution systems with reduced parasitic loading effects are provided. A reference clock is frequency-divided to produce a lower frequency clock...
US-7,528,624 Output buffer and method having a supply voltage insensitive slew rate
An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages....
US-7,528,536 Protective layer for corrosion prevention during lithography and etch
Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion...
US-7,528,491 Semiconductor components and assemblies including vias of varying lateral dimensions
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a...
US-7,528,477 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,528,463 Semiconductor on insulator structure
An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than...
US-7,528,440 Vertical gain cell
A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source...
US-7,528,439 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,528,435 Semiconductor constructions
The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions...
US-7,528,430 Electronic systems
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second...
US-7,528,424 Integrated circuitry
This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer...
US-7,528,401 Agglomeration elimination for metal sputter deposition of chalcogenides
A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and...
US-7,528,064 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,...
US-7,528,043 Scalable gate and storage dielectric
Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a...
US-7,528,037 Flash memory having a high-permittivity tunnel dielectric
A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages....
US-7,528,007 Methods for assembling semiconductor devices and interposers
A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that...
US-7,527,693 Apparatus for improved delivery of metastable species
The invention includes a deposition system having a reservoir for containment of a metastable specie connected to a deposition chamber. The system includes a...
US-7,527,545 Methods and tools for controlling the removal of material from microfeature workpieces
Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method...
US-7,526,795 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be...
US-7,526,713 Low power cost-effective ECC memory system and method
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The...
US-7,526,709 Error detection and correction in a CAM
An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not...
US-7,526,704 Testing system and method allowing adjustment of signal transmit timing
A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing...
US-7,526,095 Audio volume control for computer systems
A computer system includes an audio chip to generate audio signals at a target volume level to be emitted as audio output by speakers. Also included in the...
US-7,525,842 Increased NAND flash memory read throughput
A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and...
US-7,525,841 Programming method for NAND flash
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells...
US-7,525,671 Registration method and apparatus therefor
The present invention relates to a method to determine a position of at least one mark provided on a substrate, comprising the actions of: detecting a first mark...
US-7,525,458 Method and apparatus for converting parallel data to serial data in high speed applications
A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data...
US-7,525,379 Low voltage CMOS differential amplifier
There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS...
US-7,525,354 Local coarse delay units
Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed...
US-7,525,352 Current differential buffer
A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that...
US-7,525,332 On-chip substrate regulator test mode
An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating...
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