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Patent # Description
US-7,560,336 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,560,335 Memory device transistors
Method and device embodiments are described for fabricating MOSFET transistors in a semiconductor also containing non-volatile floating gate transistors. MOSFET...
US-7,560,305 Apparatus and method for high density multi-chip structures
Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures...
US-7,560,017 Methods and apparatus for electrically detecting characteristics of a microelectronic substrate and/or...
Methods and apparatuses for detecting characteristics of a microelectronic substrate. A method in accordance with an embodiment of the invention includes...
US-7,559,773 Electrical connecting apparatus
The present invention prevents damage of adjacent mounting portions caused by heat at the time of mounting of contactors and further reduces the arrangement...
US-RE40,842 Memory elements and methods for making same
Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and...
US-7,558,142 Method and system for controlling refresh to avoid memory cell data losses
A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a...
US-7,558,133 System and method for capturing data signals using a data strobe signal
A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system...
US-7,558,131 NAND system with a data write frequency greater than a command-and-address-load frequency
The invention provides methods and apparatus. A NAND flash memory device receives command and address signals at a first frequency and a data signal at a second...
US-7,558,130 Adjustable drive strength apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die...
US-7,558,125 Input buffer and method with AC positive feedback, and a memory device and computer system using same
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative...
US-7,558,102 Device and method having a memory array storing each bit in multiple memory cells
A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store "1" and "0"...
US-7,557,631 Voltage and temperature compensation delay system and method
A delay circuit provides a voltage and temperature compensated delayed output signal. The delay circuit includes a first delay stage that receives an input...
US-7,557,628 Method and apparatus for digital phase generation at high frequencies
An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N...
US-7,557,620 System and method for controlling input buffer biasing current
A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a...
US-7,557,603 Method and apparatus for output driver calibration, and memory devices and system embodying same
A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit...
US-7,557,601 Memory module and method having improved signal routing topology
A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology....
US-7,557,593 Probe for electrical test and probe assembly
A probe for electrical test comprises a probe body having a base end attached to a support base plate through a solder and a front end continuous with said base...
US-7,557,454 Assemblies with bond pads of two or more semiconductor devices electrically connected to the same surface of a...
A semiconductor device includes two or more semiconductor devices with bond pads that are electrically connected to the same, single surface of a plurality of...
US-7,557,452 Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating...
A conductive structure configured to connect a contact pad of a semiconductor device with a corresponding contact pad of a substrate. The conductive structure...
US-7,557,443 Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of...
US-7,557,420 Low temperature process for polysilazane oxidation/densification
Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed....
US-7,557,345 Integrated circuit chips, apparatuses for obtaining backscatter data from samples, methods of backscatter...
Some embodiments include methods for fabricating an alpha particle emitter and detector associated with an integrated circuit chip. Some embodiments include an...
US-7,557,048 Methods of forming semiconductor constructions
The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can...
US-7,557,047 Method of forming a layer of material using an atomic layer deposition process
Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative...
US-7,557,032 Silicided recessed silicon
Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the...
US-7,557,024 Single poly CMOS imager
More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a...
US-7,557,015 Methods of forming pluralities of capacitors
The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a...
US-7,557,013 Methods of forming a plurality of capacitors
A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises...
US-7,557,006 Methods of forming field effect transistors
A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided...
US-7,557,002 Methods of forming transistor devices
Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over...
US-7,557,001 Semiconductor processing methods
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a...
US-7,556,897 Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-RE40,819 Semiconductor device with improved bond pads
A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and...
US-7,555,358 Process and method for continuous, non lot-based integrated circuit manufacturing
A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes:...
US-7,554,858 System and method for reducing pin-count of memory devices, and memory device testers for same
Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output...
US-7,554,852 Method of erasing flash memory with pre-programming memory cells only in the presence of a cell leakage
Some embodiments include converting a plurality of memory cells into a first logic state, and converting the plurality of memory cells into a second logic state...
US-7,554,846 Select gate transistors and methods of operating the same
Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of...
US-7,554,829 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,554,589 Redundancy in column parallel or row architectures
A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row...
US-7,554,375 Delay line circuit
Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are...
US-7,554,200 Semiconductor devices including porous insulators
Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed...
US-7,554,171 Semiconductor constructions
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and...
US-7,554,161 HfAlO.sub.3 films for gate dielectrics
A dielectric film containing HfAlO.sub.3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide...
US-7,554,142 Ultrashallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,554,071 Method and apparatus providing pixel array having automatic light control pixels and image capture pixels
A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC)...
US-7,553,770 Reverse masking profile improvements in high aspect ratio etch
A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of...
US-7,553,735 Scalable high performance non-volatile memory cells using multi-mechanism carrier transport
A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate...
US-7,553,699 Method of fabricating microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality...
US-7,553,697 Multiple chip semiconductor package
A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice,...
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