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Patent # Description
US-7,518,422 Switched capacitor for a tunable delay circuit
A method and apparatus is provided for providing a fine delay by switching on a capacitor delay. A coarse delay and/or a fine delay are implemented upon a...
US-7,518,302 Method of fabricating field emission arrays employing a hard mask to define column lines and another mask to...
Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive...
US-7,518,246 Atomic layer deposition of CeO.sub.2/Al.sub.2O.sub.3 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer...
US-7,518,237 Microfeature systems including adhered microfeature workpieces and support members
Methods and systems for adhering microfeature workpieces to support members are disclosed. A method in accordance with one embodiment of the invention includes...
US-7,518,227 Multiple die stack apparatus employing T-shaped interposer elements
Multiple integrated circuit devices in a stacked configuration that use a spacing element for allowing increased device density and increased thermal conduction...
US-7,518,223 Semiconductor devices and semiconductor device assemblies including a nonconfluent spacer layer
A semiconductor device that includes at least one nonconfluent spacer layer on at least one surface thereof. The at least one nonconfluent spacer layer at least...
US-7,518,212 Graded Ge.sub.xSe.sub.100-x concentration in PCRAM
The present invention provides a design for a PCRAM element which incorporates multiple metal-containing germanium-selenide glass layers of diverse...
US-7,518,184 DRAM access transistor
Self-aligned recessed gate structures and method of formation are disclosed. Field oxide areas for isolation are first formed in a semiconductor substrate. A...
US-7,518,182 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,518,174 Memory cell and method for forming the same
A semiconductor memory cell structure having 4F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and...
US-7,517,804 Selective etch chemistries for forming high aspect ratio features and associated structures
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide...
US-7,517,798 Methods for forming through-wafer interconnects and structures resulting therefrom
The present invention relates to methods for forming through-wafer interconnects in semiconductor substrates and the resulting structures. In one embodiment, a...
US-7,517,797 Carrier for wafer-scale package, wafer-scale package including the carrier, and methods
A carrier for use in a chip-scale package includes a semiconductor substrate with a plurality of apertures formed therethrough. The apertures of the carrier are...
US-7,517,786 Methods of forming wire bonds for semiconductor constructions
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
US-7,517,783 Molybdenum-doped indium oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain...
US-7,517,758 Method of forming a vertical transistor
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,517,754 Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically...
US-7,517,753 Methods of forming pluralities of capacitors
The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes anodically...
US-7,517,749 Method for forming an array with polysilicon local interconnects
Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature...
US-7,517,744 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,517,743 Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,517,704 MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the...
US-7,517,558 Methods for positioning carbon nanotubes
The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment,...
US-7,516,363 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,516,300 Active memory processing array topography and method
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying...
US-7,516,281 On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes
A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of...
US-7,516,271 Obtaining search results based on match signals and search width
Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM...
US-7,515,501 Memory architecture having local column select lines
A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections...
US-7,515,485 External clock tracking pipelined latch scheme
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data...
US-7,515,481 Memory block erasing in a flash memory device
The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory...
US-7,515,188 Method and system for reducing mismatch between reference and intensity paths in analog to digital converters...
A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied...
US-7,514,991 High accuracy current mode duty cycle and phase placement sampling circuit
A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock...
US-7,514,982 Methods, devices and systems for sensing the state of fuse devices
A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the...
US-7,514,979 De-emphasis system and method for coupling digital signals through capacitively loaded lines
A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals...
US-7,514,954 Method and apparatus for output driver calibration
An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by...
US-7,514,945 Systems configured for utilizing semiconductor components
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,514,776 Semiconductor/printed circuit board assembly, and computer system
A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate...
US-7,514,366 Methods for forming shallow trench isolation
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a...
US-7,514,324 Selective epitaxy in vertical integrated circuit
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are...
US-7,514,291 Methods relating to singulating semiconductor wafers and wafer scale assemblies
Methods relating to singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding...
US-7,513,182 Integrated circuit package separators
Integrated circuit package separator for separating integrated circuit packages from a board. A base having a plurality of pins extending upwardly therefrom is...
US-7,512,910 Integrated circuit design using charge pump modeling
Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of...
US-7,512,909 Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
US-7,512,763 Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has...
US-7,512,507 Die based trimming
Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the...
US-7,512,170 Method of forming mirrors by surface transformation of empty spaces in solid state materials
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,512,029 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-7,512,025 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,512,019 High speed digital signal input buffer and method using pulsed positive feedback
An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit...
US-7,511,994 MEM suspended gate non-volatile memory
A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing...
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