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Patent # Description
US-7,517,744 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,517,743 Fully-depleted (FD) (SOI) MOSFET access transistor and method of fabrication
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,517,704 MRAM layer having domain wall traps
A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the...
US-7,517,558 Methods for positioning carbon nanotubes
The present invention is generally directed to a system for controlling placement of nanoparticles, and methods of using same. In one illustrative embodiment,...
US-7,516,363 System and method for on-board diagnostics of memory modules
A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub...
US-7,516,300 Active memory processing array topography and method
An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying...
US-7,516,281 On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes
A method and apparatus for controlling the on-die termination of a memory system. The method comprises snooping a command bus in response to a first plurality of...
US-7,516,271 Obtaining search results based on match signals and search width
Content addressable memory (CAM) in which search results such as an address code and an array match signal can be obtained for multiple search widths. The CAM...
US-7,515,501 Memory architecture having local column select lines
A memory architecture for an array of memory cells having a plurality of sections of memory and a plurality of regions disposed between the plurality of sections...
US-7,515,485 External clock tracking pipelined latch scheme
A flash memory including a first latch having at least one external input to receive at least one command, at least one memory address, and a plurality of data...
US-7,515,481 Memory block erasing in a flash memory device
The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory...
US-7,515,188 Method and system for reducing mismatch between reference and intensity paths in analog to digital converters...
A circuit for reducing a mismatch between a reference path to which a reference voltage is applied and an intensity path to which an intensity voltage is applied...
US-7,514,991 High accuracy current mode duty cycle and phase placement sampling circuit
A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock...
US-7,514,982 Methods, devices and systems for sensing the state of fuse devices
A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the...
US-7,514,979 De-emphasis system and method for coupling digital signals through capacitively loaded lines
A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals...
US-7,514,954 Method and apparatus for output driver calibration
An output driver calibration circuit determines calibration values for configuring adjustable impedance output drivers. Output drivers are calibrated by...
US-7,514,945 Systems configured for utilizing semiconductor components
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,514,776 Semiconductor/printed circuit board assembly, and computer system
A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate...
US-7,514,366 Methods for forming shallow trench isolation
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a...
US-7,514,324 Selective epitaxy in vertical integrated circuit
Integrated circuit components are described that are formed using selective epitaxy such that the integrated circuit components, such as transistors, are...
US-7,514,291 Methods relating to singulating semiconductor wafers and wafer scale assemblies
Methods relating to singulation of dice from semiconductor wafers. Trenches or channels are formed in the bottom surface of a semiconductor wafer, corresponding...
US-7,513,182 Integrated circuit package separators
Integrated circuit package separator for separating integrated circuit packages from a board. A base having a plurality of pins extending upwardly therefrom is...
US-7,512,910 Integrated circuit design using charge pump modeling
Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of...
US-7,512,909 Read strobe feedback in a memory system
A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is...
US-7,512,763 Transparent SDRAM in an embedded environment
A transparent memory array has a processor and a plurality of memory banks, each memory bank being directly connected to the processor. The memory array has...
US-7,512,507 Die based trimming
Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the...
US-7,512,170 Method of forming mirrors by surface transformation of empty spaces in solid state materials
A multi-layered reflective mirror formed of spaced-apart plate-shaped empty space patterns formed within a substrate is disclosed. The plurality of plate-shaped...
US-7,512,029 Method and apparatus for managing behavior of memory devices
A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it...
US-7,512,025 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,512,019 High speed digital signal input buffer and method using pulsed positive feedback
An input buffer generates an output signal corresponding to a digital input signal. The input buffer is coupled to a feedback circuit. The feedback circuit...
US-7,511,994 MEM suspended gate non-volatile memory
A carrier storage node such as a floating gate is formed on a moving electrode with a control gate to form a suspended gate non-volatile memory, reducing...
US-7,511,984 Phase change memory
A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing...
US-7,511,644 Variable resistance logic
A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new...
US-7,511,534 Circuits, devices, systems, and methods of operation for a linear output driver
Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages....
US-7,511,531 Temperature-compensated output buffer
A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up...
US-7,511,520 Universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,511,364 Floating lead finger on a lead frame, lead frame strip, and lead frame assembly including same
A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame...
US-7,511,363 Copper interconnect
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,511,356 Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
US-7,511,354 Well for CMOS imager and method of formation
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically...
US-7,511,341 SOI device having increased reliability and reduced free floating body effects
The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium...
US-7,511,326 ALD of amorphous lanthanide doped TiO.sub.x films
The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO.sub.x) doped with lanthanide elements, such as samarium,...
US-7,511,262 Optical device and assembly for use with imaging dies, and wafer-label imager assembly
Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including...
US-7,510,983 Iridium/zirconium oxide structure
Embodiments of an electronic apparatus and embodiments for methods of forming the electronic apparatus include a conductive layer having an iridium-based layer,...
US-7,510,966 Electrically conductive line, method of forming an electrically conductive line, and method of reducing...
The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration...
US-7,510,961 Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure
A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed...
US-7,510,954 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-7,510,897 Photodiode with self-aligned implants for high quantum efficiency and method of formation
A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an...
US-7,509,543 Circuit and method for error test, recordation, and repair
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test....
US-7,509,474 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
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