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Method and apparatus for amplifying a regulated differential signal to a
A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range...
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
Integrated circuit cooling system and method
A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a...
Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an...
Semiconductor wafer assemblies
An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming...
Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
Memory having a vertical transistor
Structures and fabrication methods for a memory are provided. The memory includes an array of memory cells, where each memory cell has a pillar extending...
Capacitor structures with oxynitride layer between capacitor plate and
capacitor dielectric layer
Methods for fuming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
Pattern generation methods and apparatuses
A method may comprise emitting electromagnetic radiation onto a workpiece and storing data describing geometrical elements in a pattern. The electromagnetic...
Compliant contact pin assembly and card system
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
Process for improving critical dimension uniformity of integrated circuit
Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In...
Structurally-stabilized capacitors and method of making of same
Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include...
Capacitor structure for two-transistor DRAM memory cell and method of
A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically...
Method of making vertical transistor structures having
vertical-surrounding-gates with self-aligned features
The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with...
Trench DRAM cell with vertical device and buried word lines
A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for...
Microlenses including a plurality of mutually adhered layers of optically
transmissive material and systems...
Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material....
Methods of forming barium strontium titanate layers
A chemical vapor deposition method of forming a barium strontium titanate comprising dielectric layer. A substrate is positioned within a reactor. Barium and...
Atomic layer deposition methods and chemical vapor deposition methods
The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave...
Semiconductor magnetic memory integrating a magnetic tunneling junction
above a floating-gate memory cell
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
Method of comparison between cache and data register for non-volatile
A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer...
Electronic device package
An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to...
Stacked microelectronic devices and methods for manufacturing
Stacked microelectronic devices and methods for manufacturing such devices. An embodiment of a microelectronic device can include a support member and a first...
Approach to avoid buckling in BPSG by using an intermediate barrier layer
A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves...
Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
Films deposited at glancing incidence for multilevel metallization
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit...
Pixel with strained silicon layer for improving carrier mobility and blue
response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
Row driver for selectively supplying operating power to imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
Method of making a semiconductor device having improved contacts
A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In...
Nickel bonding cap over copper metalized bondpads
A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the...
Method of making multichip wafer level packages and computing systems
The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and...
Die loss estimation using universal in-line metric (UILM)
A system predicts die loss for a semiconductor wafer by using a method referred to as universal in-line metric (UILM). A wafer inspection tool detects defects on...
Strained semiconductor, devices and systems and methods of formation
In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The...
Method of forming memory devices by performing halogen ion implantation
and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
Floating-gate structure with dielectric component
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within...
One-device non-volatile random access memory cell
One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a...
Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an...
Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
System and method for testing a memory for a memory failure exhibited by a
A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a...
Interleaved input signal path for multiplexed input
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment,...
Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
Power efficient memory and cards
A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a...
Techniques for implementing accurate operating current values stored in a
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
Erase operation in a flash memory device
A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the...
Method, apparatus and system relating to automatic cell threshold voltage
Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current...
Semiconductor memory device with high permeability lines interposed
between adjacent transmission lines
A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
Column-parallel sigma-delta analog-to-digital conversion for imagers
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that do not rely on the ratio of the reset and pixel voltage levels...
Circuit and method for stable fuse detection
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal...
Method and circuit for controlling pin capacitance in an electronic device
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively...
Regulated internal power supply and method
A regulated internal power supply and method are provided. According to various embodiments, a regulated internal power supply system includes a DC to DC...
Semiconductor component sealed on five sides by polymer sealing layer
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...