Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,544,584 Localized compressive strained semiconductor
One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline...
US-7,544,563 Methods of forming a plurality of capacitors
The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node...
US-7,544,559 Methods of forming semiconductor constructions
The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material...
US-7,544,554 Methods of forming gatelines and transistor devices
The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for...
US-7,544,506 System and method for heating, cooling and heat cycling on microfluidic device
An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and...
US-7,544,388 Methods of depositing materials over substrates, and methods of forming layers over substrates
The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is...
US-7,542,614 Image feature identification and motion compensation apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may estimate the magnitude of relative motion between a scene and an image capture device used to capture the...
US-7,542,336 Architecture and method for NAND flash memory
A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are...
US-7,542,319 Chalcogenide glass constant current device, and its method of fabrication and operation
The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a...
US-7,542,129 Patterning apparatuses and methods for the same
An apparatus for patterning a workpiece may include at least two spatial light modulators. The at least two spatial light modulators may receive and relay...
US-7,541,963 Variable quantization ADC for image sensors
An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system,...
US-7,541,871 Operational transconductance amplifier (OTA)
Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include...
US-7,541,851 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
US-7,541,825 Isolation circuit
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first...
US-7,541,658 Optically interactive device package array
An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls...
US-7,541,648 Electrostatic discharge (ESD) protection circuit
An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs)...
US-7,541,635 Semiconductor fabrication using a collar
In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first...
US-7,541,632 Relaxed-pitch method of aligning active area to digit line
According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at...
US-7,541,270 Methods for forming openings in doped silicon dioxide
Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma...
US-7,541,242 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,541,081 Phase change memory for archival data storage
A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a...
US-7,540,018 Data security for digital data storage
A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be...
US-7,539,921 Parity bit system for a CAM
A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status...
US-7,539,896 Repairable block redundancy scheme
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when...
US-7,539,062 Interleaved memory program and verify method, device and system
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The...
US-7,539,052 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,539,048 Method and apparatus processing variable resistance memory cell write operation
A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking...
US-7,538,880 Turbidity monitoring methods, apparatuses, and sensors
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,538,858 Photolithographic systems and methods for producing sub-diffraction-limited features
Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit....
US-7,538,801 Region-based auto gain control and auto exposure control method and apparatus
An apparatus and method for performing automatic exposure and gain control while minimizing oscillations as well as providing a good response time, for example,...
US-7,538,702 Quantizing circuits with variable parameters
Systems, methods, and devices, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a...
US-7,538,590 Methods and apparatus for dividing a clock signal
There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true...
US-7,538,572 Off-chip driver apparatus, systems, and methods
Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis...
US-7,538,413 Semiconductor components having through interconnects
A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated...
US-7,538,392 Pseudo SOI substrate and associated semiconductor devices
The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method...
US-7,538,389 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,538,372 Twin p-well CMOS imager
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in...
US-7,538,036 Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
US-7,538,028 Barrier layer, IC via, and IC line forming methods
A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and...
US-7,538,001 Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
US-7,537,994 Methods of forming semiconductor devices, assemblies and constructions
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another...
US-7,537,966 Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer
A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing...
US-7,537,804 ALD methods in which two or more different precursors are utilized with one or more reactants to form materials...
In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M.sub.2-M.sub.1-R- and...
US-7,537,511 Embedded fiber acoustic sensor for CMP process endpoint
Devices, systems and methods for monitoring characteristics of semiconductor substrates and workpieces during planarization and for endpointing planarization...
US-7,536,618 Wide frequency range signal generator and method, and integrated circuit test system using same
A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a...
US-7,535,759 Memory system with user configurable density/performance option
The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple...
US-7,535,695 DRAM cells and electronic systems
The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and...
US-7,535,623 SLM addressing methods and apparatuses
A spatial light modulator may include a plurality of deflectable modulating elements. Each of the deflectable modulating elements may further include a support...
US-7,535,282 Dynamic well bias controlled by Vt detector
The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the...
US-7,535,281 Reduced time constant charge pump and method for charging a capacitive load
A charge pump and method converts an input voltage to a boosted voltage having a magnitude or polarity that is different from that of the input voltage. The...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.