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Patent # Description
US-7,539,062 Interleaved memory program and verify method, device and system
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The...
US-7,539,052 Non-volatile multilevel memory cell programming
Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number...
US-7,539,048 Method and apparatus processing variable resistance memory cell write operation
A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking...
US-7,538,880 Turbidity monitoring methods, apparatuses, and sensors
Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided....
US-7,538,858 Photolithographic systems and methods for producing sub-diffraction-limited features
Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit....
US-7,538,801 Region-based auto gain control and auto exposure control method and apparatus
An apparatus and method for performing automatic exposure and gain control while minimizing oscillations as well as providing a good response time, for example,...
US-7,538,702 Quantizing circuits with variable parameters
Systems, methods, and devices, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a...
US-7,538,590 Methods and apparatus for dividing a clock signal
There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true...
US-7,538,572 Off-chip driver apparatus, systems, and methods
Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis...
US-7,538,413 Semiconductor components having through interconnects
A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated...
US-7,538,392 Pseudo SOI substrate and associated semiconductor devices
The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method...
US-7,538,389 Capacitorless DRAM on bulk silicon
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of...
US-7,538,372 Twin p-well CMOS imager
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in...
US-7,538,036 Methods of forming openings, and methods of forming container capacitors
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
US-7,538,028 Barrier layer, IC via, and IC line forming methods
A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and...
US-7,538,001 Transistor gate forming methods and integrated circuits
A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal...
US-7,537,994 Methods of forming semiconductor devices, assemblies and constructions
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another...
US-7,537,966 Method for fabricating board on chip (BOC) semiconductor package with circuit side polymer layer
A method for fabricating a BOC package includes the steps of providing a semiconductor die having planarized bumps encapsulated in a polymer layer, and providing...
US-7,537,804 ALD methods in which two or more different precursors are utilized with one or more reactants to form materials...
In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M.sub.2-M.sub.1-R- and...
US-7,537,511 Embedded fiber acoustic sensor for CMP process endpoint
Devices, systems and methods for monitoring characteristics of semiconductor substrates and workpieces during planarization and for endpointing planarization...
US-7,536,618 Wide frequency range signal generator and method, and integrated circuit test system using same
A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a...
US-7,535,759 Memory system with user configurable density/performance option
The memory system has one or more memory dies coupled to a processor or other system controller. Each die has a separate memory array organized into multiple...
US-7,535,695 DRAM cells and electronic systems
The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and...
US-7,535,623 SLM addressing methods and apparatuses
A spatial light modulator may include a plurality of deflectable modulating elements. Each of the deflectable modulating elements may further include a support...
US-7,535,282 Dynamic well bias controlled by Vt detector
The p- well back bias for NCH transistors in a DRAM sense amplifier circuit is dynamically adjusted. Preferably, during sensing, the p- well back bias for the...
US-7,535,281 Reduced time constant charge pump and method for charging a capacitive load
A charge pump and method converts an input voltage to a boosted voltage having a magnitude or polarity that is different from that of the input voltage. The...
US-7,535,250 Output impedance calibration circuit with multiple output driver models
A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area...
US-7,535,112 Semiconductor constructions comprising multi-level patterns of radiation-imageable material
The invention includes a semiconductor construction having a wire bonding region associated with a metal-containing layer, and having radiation-imageable...
US-7,535,103 Structures and methods to enhance copper metallization
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a...
US-7,535,054 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,535,048 NROM memory cell, memory array, related devices and methods
An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function...
US-7,535,047 Semiconductor device containing an ultra thin dielectric film or dielectric layer
An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A...
US-7,534,982 Reduced imager crosstalk and pixel noise using extended buried contacts
Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer...
US-7,534,694 Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
US-7,534,681 Memory device fabrication
The invention provides methods of fabricating memory devices. One embodiment forms a bulk insulation layer overlying a plurality of source/drain regions formed...
US-7,534,660 Methods for assembly and packaging of flip chip configured dice with interposer
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor...
US-7,533,665 Dicing saw blade positioning apparatus and methods independent of blade thickness via constrained biasing elements
An apparatus for positioning dicing saw blades at a fixed axial distance from one another independent of the thicknesses of the saw blades, where the saw blade...
US-7,533,350 Multiple operating system quick boot utility
A computerized user interface for assisting a computer user selects a default operating system for a computer. The computerized interface operates during a...
US-7,533,213 Memory hub and method for memory system performance monitoring
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,532,532 System and method for hidden-refresh rate modification
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a...
US-7,532,524 Bitline exclusion in verification operation
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting...
US-7,532,517 Non-volatile one time programmable memory
A verify operation is performed on the one time programmable memory block to determine if it has been programmed. If any bits have been programmed, further...
US-7,532,053 Phase interpolation apparatus, systems, and methods
A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal...
US-7,532,020 Probe assembly
A probe assembly having a plurality of probes, each of which is secured to an anchor portion on a probe base plate, extends in a direction apart from the anchor...
US-7,531,906 Flip chip packaging using recessed interposer terminals
A method and apparatus for packaging a semiconductor die with an interposer substrate. A semiconductor device assembly includes a conductively bumped...
US-7,531,869 Lanthanum aluminum oxynitride dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of...
US-7,531,453 Microelectronic devices and methods for forming interconnects in microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
US-7,531,443 Method and system for fabricating semiconductor components with through interconnects and back side...
A method for fabricating semiconductor components includes the step of providing a semiconductor substrate having a circuit side, a back side, a plurality of...
US-7,531,421 Semiconductor capacitor structure and method to form same
A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride...
US-7,531,395 Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising...
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