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Persistent memory for processor main memory
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A...
Memory cells, methods of fabrication, semiconductor device structures, and
Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one...
Semiconductor device with strained channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
Semiconductor device including a contact plug with barrier materials
Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a...
Semiconductor die assemblies and semiconductor devices including same
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice...
Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
Systems and methods involving managing a problematic memory cell
Subject matter described pertains to managing problematic memory cells in a memory array.
Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
Programming a memory cell to a voltage to indicate a data value and after
a relaxation time programming the...
A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is...
Apparatuses and operation methods associated with resistive memory cell
arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
Apparatuses and methods for controlling a clock signal provided to a clock
Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command...
Apparatus and method for buffered write commands in a memory
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after...
I/O circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state...
Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
Security memory access method and apparatus
Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory...
Package including an underfill material in a portion of an area between
the package and a substrate or another...
Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first...
Bitwise operations and apparatus in a multi-level system
A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for...
Magnetic tunnel junctions
A magnetic tunnel junction includes a conductive first magnetic electrode that includes magnetic recording material. A conductive second magnetic electrode is...
Methods of forming magnetic memory cells
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods...
Impact ionization devices, and methods of forming impact ionization
Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of...
Semiconductor devices including vertical memory cells and methods of
A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or...
Solid state transducer devices, including devices having integrated
electrostatic discharge protection, and...
Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment,...
Methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material....
Sensing memory cells coupled to different access lines in different blocks
of memory cells
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the...
Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
Memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
Apparatuses, integrated circuits, and methods for testmode security
Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store...
Dynamic burst length output control in a memory
A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by...
Electric high pressure decompressor
Memory cells, methods of operation and fabrication, semiconductor device
structures, and memory systems
A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be...
Method and apparatus for reducing signal loss in a photo detector
Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect...
Integrated circuitry components, switches, and memory cells
A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair....
Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
Memory with temperature coefficient trimming
A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a...
Apparatuses, sense circuits, and methods for compensating for a wordline
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data...
Memory refresh methods, memory section control circuits, and apparatuses
Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a...
Power consumption control
The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information...
Error correction operations in a memory device
Memory devices configured to determine if an error exists in read data and to respond to determined errors, as well as methods of operating such memory devices....
Apparatus and methods for leakage current reduction in integrated circuits
This disclosure relates to leakage current reduction in integrated circuits (ICs). In one aspect, an IC can include a digital logic circuit and a polarization...
Semiconductor apparatus including output buffer
An output circuit includes first, second and third transistors. The first transistor includes first and second diffusion layers. The third transistor includes...
Confined resistance variable memory cells and methods
Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory...
Array of cross point memory cells and methods of forming an array of cross
point memory cells
An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and...
Semiconductor structures including bodies of semiconductor material and
methods of forming same
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from...
Apparatuses and methods for forming multiple decks of memory cells
Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck...
Stacked packaged integrated circuit devices, and methods of making same
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
Discontinuous patterned bonds for semiconductor devices and associated
systems and methods
Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second...