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Patent # Description
US-9,508,628 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a...
US-9,508,591 Stair step formation using at least two masks
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a...
US-9,508,440 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-9,508,427 Apparatuses and methods including supply current in memory
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the...
US-9,508,426 Program-disturb management for phase change memory
Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a...
US-9,508,417 Methods and apparatuses for controlling timing paths and latency based on a loop delay
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An...
US-9,508,409 Apparatuses and methods for implementing masked write commands
Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and...
US-9,508,407 Wiring configuration of a bus system and power wires in a memory chip
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective...
US-9,507,104 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,503,066 Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes...
US-9,503,019 Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
US-9,502,650 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,502,642 Magnetic tunnel junctions, methods used while forming magnetic tunnel junctions, and methods of forming...
A method used while forming a magnetic tunnel junction comprises forming non-magnetic tunnel insulator material over magnetic electrode material. The tunnel...
US-9,502,516 Recessed access devices and gate electrodes
Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are...
US-9,502,369 Semiconductor devices and packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
US-9,502,314 Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus
Disclosed herein is a method for manufacturing a tested apparatus that includes forming a stacked structure that includes a plurality of first semiconductor...
US-9,502,256 ZrAION films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices....
US-9,502,125 Concurrently reading first and second pages of memory cells having different page addresses
In an embodiment, a first page of memory cells in a first memory plane is read concurrently with a second page of memory cells in a second memory plane. The...
US-9,502,101 Two-part programming methods
A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be...
US-9,502,083 Output buffer circuit with low sub-threshold leakage current
A device includes a cutting circuit that is coupled between power supply lines in series with first and second output circuits which drive an output terminal in...
US-9,501,705 Methods and apparatuses for reducing power consumption in a pattern recognition processor
Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of...
US-9,501,222 Protection zones in virtualized physical addresses for reconfigurable memory systems using a memory abstraction
Systems and methods define a memory system using an abstracted memory protocol that enables virtual to physical mapping of memory address requests at an...
US-9,501,131 Methods and systems for power management in a pattern recognition processing system
A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows...
US-9,499,907 Methods of forming material over a substrate and methods of forming capacitors
A method of forming a material over a substrate includes performing at least one iteration of the following temporally separated ALD-type sequence. First, an...
US-9,496,495 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,496,491 Methods of forming a metal chalcogenide material and related methods of forming a memory cell
A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting...
US-9,496,454 Solid state optoelectronic device with plated support substrate
A vertical solid state lighting (SSL) device is disclosed. In one embodiment, the SSL device includes a light emitting structure formed on a growth substrate....
US-9,496,355 Conductive nanoparticles
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge storage units in...
US-9,496,050 Methods and apparatuses for stacked device testing
Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the...
US-9,496,023 Comparison operations on logical representations of values in memory
One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first...
US-9,490,631 Over-limit electrical condition protection circuits and methods
Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit...
US-9,490,425 Semiconductor constructions and memory arrays
Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive...
US-9,490,239 Solid state transducers with state detection, and associated systems and methods
Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system in accordance with a particular...
US-9,490,220 Redistribution structures for microfeature workpieces
Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having...
US-9,490,025 Methods of programming memory devices
Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of...
US-9,489,302 Control arrangements and methods for accessing block oriented nonvolatile memory
A memory system digitally communicates with a host device to provide data storage capacity for the host device. The memory system includes at least one module...
US-9,489,301 Memory systems
Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile...
US-D770,986 Plunger housing body
US-D770,985 Electric contact
US-9,484,536 Memory cells, memory arrays, and methods of forming memory cells and arrays
Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed...
US-9,484,534 Via formation for cross-point memory
Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a...
US-9,484,378 Semiconductor devices including back-side integrated circuitry
Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the...
US-9,484,326 Apparatuses having stacked devices and methods of connecting dice stacks
Various embodiments include apparatuses having stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack...
US-9,484,225 Method for packaging circuits
A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base...
US-9,484,196 Semiconductor structures including liners comprising alucone and related methods
A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and...
US-9,484,101 Methods of programming memories
Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of...
US-9,484,100 Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
US-9,484,088 Permutational memory cells
Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the...
US-9,484,074 Current mode sense amplifier with load circuit for performance stability
Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled...
US-9,484,070 Apparatuses supporting multiple interface types and methods of operating the same
Apparatuses supporting multiple interface types and methods operating the same are described. One such method can include providing, to a memory device, a first...
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