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Patent # Description
US-1,009,0317 Methods and apparatuses having memory cells including a monolithic semiconductor channel
Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of...
US-1,009,0310 Memory devices having select gates with P type bodies, memory strings having separate source lines and methods
Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region...
US-1,009,0283 Methods and systems for improving power delivery and signaling in stacked semiconductor devices
Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the...
US-1,009,0282 Semiconductor device assemblies with lids including circuit elements
A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a...
US-1,009,0177 Cold fluid semiconductor device release during pick and place operations, and associated systems and methods
Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies...
US-1,009,0064 Timing based arbiter systems and circuits for ZQ calibration
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips....
US-1,009,0053 Apparatus, systems, and methods to operate a memory
Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing...
US-1,009,0052 Sequential write and sequential write verify in memory device
Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory...
US-1,009,0051 Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings...
US-1,009,0050 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-1,009,0026 Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories
In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to...
US-1,009,0024 Memory device including current generator plate
Some embodiments include an apparatus and methods using a first conductive material located in a first level of an apparatus (e.g., a memory device); a second...
US-1,008,9359 Memory devices for pattern matching
Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and...
US-1,008,9250 State change in systems having devices coupled in a chained configuration
The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of...
US-1,008,9242 Memory management for a hierarchical memory system
Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual...
US-1,008,9221 Systems and methods for memory system management based on information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
US-1,008,9086 Method and apparatus for compiling regular expressions
Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between...
US-1,008,9043 Apparatus and methods for a distributed memory system including memory nodes
Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system...
US-1,008,8862 Apparatuses and methods for power regulation based on input power
Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit...
US-1,008,7440 Device for preparation and analysis of nucleic acids
An integrated "lab-on-a-chip" microfluidic device performs nucleic acid sample preparation and diagnostic analysis from test samples containing cells and/or...
US-1,008,5315 Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
US-1,008,4974 Ambient infrared detection in solid state sensors
An image sensor device has a first region configured to sense only infrared illumination and a second region configured to not sense visible and infrared...
US-1,008,4487 Apparatuses and methods for erasure-assisted ECC decoding
One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second...
US-1,008,4129 Method and apparatus providing multi-planed array memory device
A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions....
US-1,008,4114 Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
US-1,008,4084 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-1,008,4016 Cross-point memory and methods for fabrication of same
A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The...
US-1,008,3984 Integrated structures and methods of forming integrated structures
Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A...
US-1,008,3981 Memory arrays, and methods of forming memory arrays
Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends...
US-1,008,3973 Apparatuses and methods for reading memory cells
Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line...
US-1,008,3941 Stacked semiconductor dies with selective capillary under fill
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a...
US-1,008,3937 Semiconductor devices and packages and methods of forming semiconductor device packages
Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a...
US-1,008,3931 Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes...
US-1,008,3751 Data state synchronization
The present disclosure includes apparatuses, and methods for data state synchronization. An example apparatus includes performing a write operation to store a...
US-1,008,3745 Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric...
US-1,008,3744 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-1,008,3734 Memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,008,3733 Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a...
US-1,008,3732 Memory cell imprint avoidance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a...
US-1,008,3731 Memory cell sensing with storage component isolation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection...
US-1,008,3727 Apparatuses and methods for concurrently accessing different memory planes of a memory
Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a...
US-1,008,3725 Asynchronous/synchronous interface
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling...
US-1,008,3723 Apparatuses and methods for sharing transmission vias for memory devices
Apparatuses and methods for transmitting die state information between a plurality of dies are described. An example apparatus includes: a plurality of dies,...
US-1,008,3265 Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing...
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the...
US-1,008,3122 Transactional memory
Subject matter disclosed herein relates to techniques to perform transactions using a memory device.
US-1,008,3119 Memory having a static cache and a dynamic cache
The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first...
US-1,008,3078 Method and apparatus for a volume management system in a non-volatile memory device
Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks...
US-1,008,2976 Method and apparatus for configuring write performance for electrically writable memory devices
Methods and systems are provided that may include a nonvolatile memory to store information, where the nonvolatile memory is associated with a configuration...
US-1,008,2975 Obfuscation-enhanced memory encryption
The present disclosure includes apparatuses and methods for obfuscation-enhanced memory encryption. An example method comprises performing a write operation,...
US-1,008,2964 Data caching for ferroelectric memory
Methods, systems, and devices for operating a memory device are described. One method includes caching data of a memory cell at a sense amplifier of a row...
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