Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,473,956 Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,473,662 Metal-doped alumina and layers thereof
A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,473,645 Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate
The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and...
US-7,473,644 Method for forming controlled geometry hardmasks including subresolution elements
Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of...
US-7,473,637 ALD formed titanium nitride films
The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices....
US-7,473,615 Semiconductor processing methods
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can...
US-7,473,613 Terraced film stack
A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses...
US-7,473,596 Methods of forming memory cells
An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor...
US-7,473,582 Method for fabricating semiconductor component with thinned substrate having pin contacts
A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor...
US-7,472,392 Method for load balancing an n-dimensional array of parallel processing elements
One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of...
US-7,472,248 Techniques for generating serial presence detect contents
Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are...
US-7,471,565 Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
US-7,471,538 Memory module, system and method of making same
A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices...
US-7,471,535 Programable identification circuitry
An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate...
US-7,471,228 Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,471,227 Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second...
US-7,471,130 Graduated delay line for increased clock skew correction circuit operating range
Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped...
US-7,471,095 Electrical connecting apparatus and method for use thereof
An electrical connecting apparatus is used for electrical inspection of a device under test having electrodes each of which a recess is formed on a flat upside....
US-7,470,882 Reduction in size of column sample and hold circuitry in a CMOS imager
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of...
US-7,470,638 Systems and methods for manipulating liquid films on semiconductor substrates
A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a...
US-7,470,635 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry, methods of...
This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation,...
US-7,470,632 Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer...
US-7,470,631 Methods for fabricating residue-free contact openings
A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures...
US-7,470,628 Etching methods
Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide...
US-7,470,625 Method of plasma etching a substrate
A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to...
US-7,470,606 Masking methods
The invention includes masking methods. In one implementation, a masking material which includes boron doped amorphous carbon is formed over a feature formed on...
US-7,470,590 Methods of forming semiconductor constructions
The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending...
US-7,470,583 Method of improved high K dielectric-polysilicon interface for CMOS devices
Methods for forming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are...
US-7,470,576 Methods of forming field effect transistor gate lines
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,470,563 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such...
A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection...
US-7,470,552 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,470,344 Chemical dispensing system for semiconductor wafer processing
A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively...
US-D583,856 Ink ribbon cassette
US-7,468,922 Apparatus and method for dynamically repairing a semiconductor memory
An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing...
US-7,468,623 Clamp circuit with fuse options
A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage...
US-7,468,610 Electrical connecting apparatus
An electrical connecting apparatus comprising: a circuit board on which a reinforcing plate is mounted and a plurality of first electric connections are...
US-7,468,559 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,468,534 Localized masking for semiconductor structure development
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical...
US-7,468,533 Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
US-7,468,323 Method of forming high aspect ratio structures
An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure...
US-7,468,108 Metal layer forming methods and capacitor electrode forming methods
A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer...
US-7,468,105 CMP cleaning composition with microbial inhibitor
An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are...
US-7,468,104 Chemical vapor deposition apparatus and deposition method
A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. A...
US-7,467,334 Method for repairing a semiconductor memory
A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row....
US-7,466,618 Current limiting antifuse programming path
Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the...
US-7,466,615 Low voltage data path and current sense amplifier
Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output...
US-7,466,606 Memory device having terminals for transferring multiple types of data
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,466,602 Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
US-7,466,600 System and method for initiating a bad block disable process in a non-volatile memory
A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid...
US-7,465,999 Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.