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| Patent # | Description |
|---|---|
| US-7,575,953 |
Stacked die with a recess in a die BGA package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. |
| US-7,574,634 |
Real time testing using on die termination (ODT) circuit A system and method to operate an electronic device, such as a memory chip, in a test mode using the device's built-in ODT (on die termination) circuit is... |
| US-7,574,466 |
Method for finding global extrema of a set of shorts distributed across an
array of parallel processing elements A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each processing... |
| US-7,574,309 |
Internal bias measure with onboard ADC for electronic devices An apparatus and method for on-chip bias measurement of an analog signals on an integrated circuit with a switchable analog-to-digital converter capable of... |
| US-7,573,752 |
NAND flash memory cell programming A flash memory device, such as a NAND flash, is described having an array of floating gate transistor memory cells arranged in a first and second addressable... |
| US-7,573,738 |
Mode selection in a flash memory device A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode... |
| US-7,573,733 |
Self-identifying stacked die semiconductor components A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a... |
| US-7,573,288 |
Dynamically adjusting operation of a circuit within a semiconductor device Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments... |
| US-7,573,276 |
Probe card layout Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater than 99% efficiency during testing of a substrate having a plurality... |
| US-7,573,136 |
Semiconductor device assemblies and packages including multiple
semiconductor device components A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of... |
| US-7,573,125 |
Methods for reducing stress in microelectronic devices and microelectronic
devices formed using such methods Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a... |
| US-7,573,121 |
Method for enhancing electrode surface area in DRAM cell capacitors Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is... |
| US-7,573,116 |
Etch aided by electrically shorting upper and lower sidewall portions
during the formation of a semiconductor... A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the... |
| US-7,573,113 |
Photodiode with ultra-shallow junction for high quantum efficiency CMOS
image sensor and method of formation A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow... |
| US-7,573,108 |
Non-planar transistor and techniques for fabricating the same A non-planar transistor and methods for fabricating the same. In certain embodiments, the transistor includes an active gate and a passive gate. The active gate... |
| US-7,573,088 |
DRAM array and electronic system The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double... |
| US-7,573,087 |
Interconnect line selectively isolated from an underlying contact plug A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and... |
| US-7,573,021 |
Method and apparatus for multiple scan rate swept wavelength laser-based
optical sensor interrogation system... The invention relates to optical sensor measurement methods that use a swept wavelength optical source to determine wavelength shift as well as to optical sensor... |
| US-7,573,006 |
Apparatus relating to the reconstruction of semiconductor wafers for
wafer-level processing Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice... |
| US-7,572,731 |
Unsymmetrical ligand sources, reduced symmetry metal-containing compounds,
and systems and methods including same The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In some... |
| US-7,572,725 |
Methods for wafer-level packaging of microelectronic devices and
microelectronic devices formed by such methods Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices. One aspect of the invention is... |
| US-7,572,710 |
Methods of forming conductive contacts to source/drain regions and methods
of forming local interconnects The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local... |
| US-7,572,695 |
Hafnium titanium oxide films Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an... |
| US-7,572,678 |
Methods of making and using a floating lead finger on a lead frame A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame... |
| US-7,572,670 |
Methods of forming semiconductor packages The invention includes semiconductor packages having a patterned substrate with openings extending therethrough, conductive circuit traces over the substrate and... |
| US-7,572,572 |
Methods for forming arrays of small, closely spaced features Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can... |
| US-7,572,385 |
Method of forming micro-lenses A method of fabricating micro-lenses is provided. A first layer is formed on a substrate. The first layer is comprised of a first material and the substrate is... |
| US-7,570,538 |
Method for writing to multiple banks of a memory device In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows... |
| US-7,570,521 |
Low power flash memory devices A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion... |
| US-7,570,504 |
Device and method to reduce wordline RC time constant in semiconductor
memory devices A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale... |
| US-7,570,293 |
Image sensor with on-chip semi-column-parallel pipeline ADCS An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple... |
| US-7,570,069 |
Resilient contact probes Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different... |
| US-7,569,983 |
Flat fluorescent lamp and liquid crystal display using the same Disclosed herein is a light source device. The light source device includes a front transparent substrate, a rear substrate, a plurality of partitions, and... |
| US-7,569,934 |
Copper interconnect An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape... |
| US-7,569,915 |
Shielding arrangement to protect a circuit from stray magnetic fields A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a... |
| US-7,569,876 |
DRAM arrays, vertical transistor structures, and methods of forming
transistor structures and DRAM arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The... |
| US-7,569,485 |
Method for an integrated circuit contact A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask... |
| US-7,569,484 |
Plasma and electron beam etching device and method Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching... |
| US-7,569,473 |
Methods of forming semiconductor assemblies Apparatus and methods are disclosed relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a... |
| US-7,569,468 |
Method for forming a floating gate memory with polysilicon local
interconnects Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature... |
| US-7,569,453 |
Contact structure This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure... |
| US-7,569,418 |
Methods for securing packaged semiconductor devices to carrier substrates A method for securing a semiconductor device to a carrier substrate includes inserting a semiconductor device with a plurality of stub contacts extending from a... |
| US-7,569,414 |
CMOS imager with integrated non-volatile memory A CMOS imager and non-volatile memory are integrated on a single substrate along with logic and support circuitry for decoding and processing optical information... |
| US-7,569,314 |
Method for quartz bump defect repair with less substrate damage A method for minimizing damage to a substrate while repairing a defect in a phase shifting mask for an integrated circuit comprising locating a bump defect in a... |
| US-7,569,311 |
Method of forming a pattern using a polarized reticle in conjunction with
polarized light Polarized reticles, photolithography systems utilizing a polarized reticle, and methods of using such a system are disclosed. A polarized reticle is formed... |
| US-7,568,970 |
Chemical mechanical polishing pads The present invention provides a deformable pad useful for chemical mechanical polishing ("CMP"), a CMP apparatus incorporating the deformable pad of the present... |
| US-7,567,848 |
Speaker apparatus and a computer system incorporating same An internal subwoofer apparatus is provided for mounting within a computer system. The computer system is a multi-media computer system that processes visual and... |
| US-7,567,477 |
Bias sensing in sense amplifiers through a voltage-coupling/decoupling
device Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The... |
| US-7,567,472 |
Memory block testing A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a... |
| US-7,567,465 |
Power saving sensing scheme for solid state memory Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a... |
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