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| Patent # | Description |
|---|---|
| US-7,491,641 |
Method of forming a conductive line and a method of forming a conductive
contact adjacent to and insulated from... This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a... |
| US-7,491,636 |
Methods for forming flexible column die interconnects and resulting
structures A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal... |
| US-7,491,608 |
Vertical transistor with horizontal gate layers Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable... |
| US-7,491,602 |
Structures and methods for improved capacitor cells in integrated circuits Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive... |
| US-7,491,570 |
Die package having an adhesive flow restriction area A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element.... |
| US-7,490,211 |
Memory hub with integrated non-volatile memory A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for... |
| US-7,490,210 |
System and method for processor with predictive memory retrieval assist A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the... |
| US-7,490,190 |
Method and system for local memory addressing in single instruction,
multiple data computer system A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random... |
| US-7,489,875 |
System and method for multiple bit optical data transmission in memory
systems The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of... |
| US-7,489,587 |
Semiconductor memory device capable of controlling clock cycle time for
reduced power consumption Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first... |
| US-7,489,575 |
Noise resistant small signal sensing circuit for a memory device Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus... |
| US-7,489,569 |
Reconstruction of signal timing in integrated circuits Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of... |
| US-7,489,568 |
Delay stage-interweaved analog DLL/PLL A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the... |
| US-7,489,564 |
256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array... |
| US-7,489,556 |
Method and apparatus for generating read and verify operations in
non-volatile memories Method and apparatus for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current... |
| US-7,489,551 |
Memory architecture and method of manufacture and operation thereof An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,... |
| US-7,489,546 |
NAND architecture memory devices and operation Non-volatile memory devices utilizing a modified NAND architecture where both ends of the NAND string of memory cells are selectively coupled to the same bit... |
| US-7,489,545 |
Memory utilizing oxide-nitride nanolaminates Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain... |
| US-7,489,543 |
Programming multilevel cell memory arrays Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one... |
| US-7,489,352 |
Wide dynamic range pinned photodiode active pixel sensor (APS) An image apparatus and method is disclosed for extending the dynamic range of an image sensor. A first linear pixel circuit produces a first pixel output signal... |
| US-7,489,184 |
Device and method for generating a low-voltage reference A voltage reference generating method, source, memory device and substrate containing the same include a voltage reference generator comprised of a bandgap... |
| US-7,489,169 |
Self-timed fine tuning control A device and system having improved timing control of input signals. Specifically, a fine delay block is provided having feedback loops therein such that the... |
| US-7,489,165 |
Method and apparatus for amplifying a regulated differential signal to a
higher voltage A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range... |
| US-7,489,041 |
Copper interconnect An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape... |
| US-7,489,034 |
Integrated circuit cooling system and method A system and method for cooling an integrated circuit is provided. One aspect of this disclosure relates to a cooling system that utilizes sound waves to cool a... |
| US-7,489,028 |
Die package Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an... |
| US-7,489,020 |
Semiconductor wafer assemblies An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming... |
| US-7,489,019 |
Epitaxial semiconductor layer and method A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include... |
| US-7,489,002 |
Memory having a vertical transistor Structures and fabrication methods for a memory are provided. The memory includes an array of memory cells, where each memory cell has a pillar extending... |
| US-7,489,000 |
Capacitor structures with oxynitride layer between capacitor plate and
capacitor dielectric layer Methods for fuming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are... |
| US-7,488,957 |
Pattern generation methods and apparatuses A method may comprise emitting electromagnetic radiation onto a workpiece and storing data describing geometrical elements in a pattern. The electromagnetic... |
| US-7,488,899 |
Compliant contact pin assembly and card system A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a... |
| US-7,488,685 |
Process for improving critical dimension uniformity of integrated circuit
arrays Methods for patterning integrated circuit (IC) device arrays employing an additional mask process for improving center-to-edge CD uniformity are disclosed. In... |
| US-7,488,665 |
Structurally-stabilized capacitors and method of making of same Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include... |
| US-7,488,664 |
Capacitor structure for two-transistor DRAM memory cell and method of
forming same A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically... |
| US-7,488,651 |
Method of making vertical transistor structures having
vertical-surrounding-gates with self-aligned features The present inventions include a vertical transistor formed by defining a channel length of the vertical-surrounding-gate field effect transistor with... |
| US-7,488,641 |
Trench DRAM cell with vertical device and buried word lines A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for... |
| US-7,488,618 |
Microlenses including a plurality of mutually adhered layers of optically
transmissive material and systems... Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material.... |
| US-7,488,514 |
Methods of forming barium strontium titanate layers A chemical vapor deposition method of forming a barium strontium titanate comprising dielectric layer. A substrate is positioned within a reactor. Barium and... |
| US-7,488,386 |
Atomic layer deposition methods and chemical vapor deposition methods The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave... |
| US-7,486,550 |
Semiconductor magnetic memory integrating a magnetic tunneling junction
above a floating-gate memory cell A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating... |
| US-7,486,530 |
Method of comparison between cache and data register for non-volatile
memory A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer... |
| US-7,485,971 |
Electronic device package An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to... |
| US-7,485,969 |
Stacked microelectronic devices and methods for manufacturing
microelectronic devices Stacked microelectronic devices and methods for manufacturing such devices. An embodiment of a microelectronic device can include a support member and a first... |
| US-7,485,961 |
Approach to avoid buckling in BPSG by using an intermediate barrier layer A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves... |
| US-7,485,948 |
Front-end processing of nickel plated bond pads A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an... |
| US-7,485,942 |
Films deposited at glancing incidence for multilevel metallization Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit... |
| US-7,485,904 |
Pixel with strained silicon layer for improving carrier mobility and blue
response in imagers An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,... |
| US-7,485,836 |
Row driver for selectively supplying operating power to imager pixel An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout... |
| US-7,485,587 |
Method of making a semiconductor device having improved contacts A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In... |
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