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| Patent # | Description |
|---|---|
| US-7,606,097 |
Array sense amplifiers, memory devices and systems including same, and
methods of operation A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output ("I/O") node and a second... |
| US-7,606,088 |
Sense amplifier circuit The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated... |
| US-7,606,075 |
Read operation for NAND memory Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated... |
| US-7,606,055 |
Memory architecture and cell design employing two access transistors An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access... |
| US-7,605,934 |
Method and system for facsimile delivery using dial-up modem pools A method and system for communicating a facsimile (fax) message over a computer network. A user initiates the sending of the fax to a recipient fax transceiver... |
| US-7,605,852 |
Real-time exposure control for automatic light control An imager and a method for real-time, non-destructive monitoring of light incident on imager pixels during their exposure to light. Real-time or present pixel... |
| US-7,605,650 |
Switched capacitor amplifier with higher gain and improved closed-loop
gain accuracy A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is... |
| US-7,605,631 |
Delay line synchronizer apparatus and method A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock... |
| US-7,605,620 |
System and method to improve the efficiency of synchronous mirror delays
and delay locked loops A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore... |
| US-7,605,611 |
Methods, devices, and systems for a high voltage tolerant buffer Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric... |
| US-7,605,417 |
Assemblies comprising magnetic elements and magnetic barrier or shielding
at least partially around the... The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First... |
| US-7,605,350 |
System for two-step resist soft bake to prevent ILD outgassing during
semiconductor processing In general, the system provides for soft baking a semiconductor wafer so that photoresist layers on the wafer are free of surface voids or craters. In... |
| US-7,605,034 |
Integrated circuit memory cells and methods of forming An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor... |
| US-7,605,033 |
Low resistance peripheral local interconnect contacts with selective wet
strip of titanium Methods for forming memory devices and integrated circuitry, for example, DRAM circuitry, structures and devices resulting from such methods, and systems that... |
| US-7,605,030 |
Hafnium tantalum oxynitride high-k dielectric and metal gates Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum... |
| US-7,605,028 |
Method of forming a memory device having a storage transistor A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion... |
| US-7,604,729 |
Methods and apparatus for selectively removing conductive material from a
microelectronic substrate Methods and apparatuses for selectively removing conductive materials from a microelectronic substrate. A method in accordance with an embodiment of the... |
| US-7,604,527 |
Methods and systems for planarizing workpieces, e.g., microelectronic
workpieces Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a... |
| US-7,603,772 |
Methods of fabricating substrates including one or more conductive vias Substrate precursor structures include a substrate blank having at least one aperture extending substantially through the substrate blank. At least a portion of... |
| US-7,603,534 |
Synchronous flash memory with status burst output A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in... |
| US-7,603,493 |
Dynamically setting burst length of memory device by applying signal to at
least one external pin during a read... One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. |
| US-7,602,876 |
Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector... |
| US-7,602,630 |
Configurable inputs and outputs for memory stacking system and method Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of... |
| US-7,602,618 |
Methods and apparatuses for transferring heat from stacked microfeature
devices Apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support... |
| US-7,602,200 |
Probe for electrical test comprising a positioning mark and probe assembly A probe for electrical test provided with positioning marks parallel to a plane where tips are provided and at a height position lower than the plane on a plane... |
| US-7,602,049 |
Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits.... |
| US-7,602,039 |
Programmable capacitor associated with an input/output pad The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus... |
| US-7,602,030 |
Hafnium tantalum oxide dielectrics A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety... |
| US-7,602,009 |
Erasable non-volatile memory device using hole trapping in high-K
dielectrics A non-volatile memory is described having memory cells with a gate dielectric. The gate dielectric is a multilayer charge trapping dielectric between a control... |
| US-7,602,001 |
Capacitorless one transistor DRAM cell, integrated circuitry comprising an
array of capacitorless one... This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An... |
| US-7,601,649 |
Zirconium-doped tantalum oxide films A dielectric film containing zirconium-doped tantalum oxide arranged as a structure of one or more monolayers and a method of fabricating such a dielectric film... |
| US-7,601,608 |
Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a... |
| US-7,601,598 |
Reverse metal process for creating a metal silicide transistor gate
structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal... |
| US-7,601,595 |
Surround gate access transistors with grown ultra-thin bodies A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid... |
| US-7,601,593 |
Flash memory with metal-insulator-metal tunneling program and erase The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is... |
| US-7,601,591 |
Method of manufacturing sidewall spacers on a memory device, and device
comprising same The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall... |
| US-7,601,586 |
Methods of forming buried bit line DRAM circuitry A method of forming buried bit line DRAM circuitry includes collectively forming a buried bit line forming trench, bit line vias extending from the bit line... |
| US-7,601,562 |
Microelectronic component assemblies having lead frames adapted to reduce
package bow The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one... |
| US-7,601,547 |
Magnetic annealing sequences for patterned MRAM synthetic
antiferromagnetic pinned layers A method is provided for fabricating a fixed layer for a MRAM device. The method includes providing the fixed layer. The fixed layer includes an ... |
| US-7,601,283 |
Methods and apparatuses for shaping a printed circuit board Methods and apparatuses for shaping a corner of a printed circuit board are disclosed. An apparatus in accordance with one embodiment includes a carrier... |
| US-7,600,314 |
Methods for installing a plurality of circuit devices A technique is provided for installing circuit components, such as memory devices, in a support, such as a socket. The device to be installed is supported in a... |
| US-7,598,181 |
Process for enhancing solubility and reaction rates in supercritical
fluids Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform... |
| US-7,598,167 |
Method of forming vias in semiconductor substrates without damaging active
regions thereof and resulting structures Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a... |
| US-7,598,165 |
Methods for forming a multiplexer of a memory device A method of forming a portion of a multiplexer of a memory device includes forming a plurality of conductive plugs on a semiconductor substrate and forming first... |
| US-7,598,134 |
Memory device forming methods A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain... |
| US-7,598,132 |
Active photosensitive structure with buried depletion layer An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a... |
| US-7,598,021 |
High resolution printing technique A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is... |
| US-7,596,729 |
Memory device testing system and method using compressed fail data A memory device testing system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read... |
| US-7,596,678 |
Method of shifting data along diagonals in a group of processing elements
to transpose the data A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the... |
| US-7,596,675 |
Memory hub architecture having programmable lane widths A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input... |
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