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| Patent # | Description |
|---|---|
| US-7,692,996 |
Method, system, and apparatus for voltage sensing and reporting A method, apparatus and system are disclosed for sensing and reporting voltage levels in a semiconductor device. One such voltage sensor and reporting device is... |
| US-7,692,984 |
System and method for initiating a bad block disable process in a
non-volatile memory A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid... |
| US-7,692,975 |
System and method for mitigating reverse bias leakage The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of... |
| US-7,692,971 |
Non-volatile multilevel memory cell programming Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method... |
| US-7,692,931 |
Microelectronic packages with leadframes, including leadframes configured
for stacked die packages, and... Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in... |
| US-7,692,705 |
Active pixel sensor with a diagonal active area An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent... |
| US-7,692,463 |
Devices and methods for controlling a slew rate of a signal line In one aspect of the invention, a method of reducing intersymbol interference on a signal line is disclosed. A state machine records previous bits that were... |
| US-7,692,437 |
Systems and methods for testing packaged microelectronic devices Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a... |
| US-7,692,210 |
Intermeshed guard bands for multiple voltage supply structures on an
integrated circuit, and methods of making same The present invention is generally directed to intermeshed guard bands for multiple voltage supply regions or structures on an integrated circuit, and methods of... |
| US-7,692,177 |
Resistance variable memory element and its method of formation A method for controlling silver doping of a chalcogenide glass in a resistance variable memory element is disclosed herein. The method includes forming a thin... |
| US-7,691,726 |
Reduced footprint packaged microelectronic components and methods for
manufacturing such microelectronic components The present disclosure describes microfeature workpieces, microelectronic component packages, and methods of forming microelectronic components and ... |
| US-7,691,722 |
Isolation trench fill using oxide liner and nitride etch back technique
with dual trench depth capability An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such... |
| US-7,691,683 |
Electrode structures and method to form electrode structures that minimize
electrode work function variation Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an... |
| US-7,691,682 |
Build-up-package for integrated circuit devices, and methods of making
same A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a... |
| US-7,691,680 |
Method of fabricating microelectronic component assemblies employing lead
frames having reduced-thickness inner... The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one... |
| US-7,689,879 |
System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors,... |
| US-7,688,653 |
Method and system for improved efficiency of synchronous mirror delays and
delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and... |
| US-7,688,635 |
Current sensing for Flash A current sensing data read/verify process and sense amplifier is described that senses memory cells of a non-volatile memory array utilizing a current sensing... |
| US-7,688,630 |
Programming memory devices A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether... |
| US-7,688,378 |
Imager method and apparatus employing photonic crystals An image sensor and a method of forming an image sensor. The image sensor includes an array of pixel cells at a surface of a substrate. Each pixel cell has a... |
| US-7,688,129 |
System and method for open-loop synthesis of output clock signals having a
selected phase relative to an input... Delay circuits are used in a manner similar to a synchronized mirror delay circuit to generate a quadrature clock signal from an input clock signal. The input... |
| US-7,688,118 |
Reduced current input buffer circuit There is provided a reduced current input buffer circuit. More specifically, in one embodiment, there is provided an input buffer circuit comprising an input... |
| US-7,688,094 |
Electrical connecting apparatus In an electrical connecting apparatus, a first guide is arranged in a plate-shaped lower base in which the contactors are arranged. The first guide has a first... |
| US-7,687,916 |
Semiconductor substrates including vias of nonuniform cross-section and
associated structures Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an... |
| US-7,687,881 |
Small electrode for phase change memories A semiconductor device is disclosed. In one embodiment, the semiconductor device includes a memory cell, which in turn includes an electrode and a phase change... |
| US-7,687,879 |
Intermediate semiconductor device structure The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal... |
| US-7,687,857 |
Integrated circuits Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate... |
| US-7,687,848 |
Memory utilizing oxide-conductor nanolaminates Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment... |
| US-7,687,844 |
Semiconductor constructions The invention includes a method of depositing a noble metal. A substrate is provided. The substrate has a first region and a second region. The first and second... |
| US-7,687,841 |
Scalable high performance carbon nanotube field effect transistor A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. The structure employs an asymmetric gate which is closer... |
| US-7,687,836 |
Capacitance noise shielding plane for imager sensor devices A conductive shield plane electrically isolating the photodiode regions from metal interconnect lines in an imager sensor device. |
| US-7,687,796 |
Method and apparatus for forming an integrated circuit electrode having a
reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a... |
| US-7,687,793 |
Resistance variable memory cells An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material... |
| US-7,687,409 |
Atomic layer deposited titanium silicon oxide films A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a... |
| US-7,687,408 |
Method for integrated circuit fabrication using pitch multiplication Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed... |
| US-7,687,406 |
Methods of eliminating pattern collapse on photoresist patterns A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The... |
| US-7,687,402 |
Methods of making optoelectronic devices, and methods of making solar
cells The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator... |
| US-7,687,358 |
Methods of forming a gated device This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device... |
| US-7,687,342 |
Method of manufacturing a memory device A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are... |
| US-7,687,329 |
Gettering of silicon on insulator using relaxed silicon germanium
epitaxial proximity layers One aspect of this disclosure relates to a method for creating proximity gettering sites in a silicon on insulator (SOI) wafer. In various embodiments of this... |
| US-7,686,874 |
Electroless plating bath composition and method of use An electroless plating composition comprising succinic acid, potassium carbonate, a source of cobalt metal ions, a reducing agent, and water is provided. An... |
| US-7,686,238 |
Powder processing method In order to manufacture the compound powder or the porous granulated substance in an efficient manner, a powder processing apparatus has an accumulating face on... |
| US-7,684,276 |
Techniques for configuring memory systems using accurate operating
parameters Techniques are disclosed for reading operating parameters from programmable elements on memory devices to configure a memory system. More specifically,... |
| US-7,684,266 |
Serial system for blowing antifuses A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from... |
| US-7,684,243 |
Reducing read failure in a memory device Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is... |
| US-7,684,237 |
Reading non-volatile multilevel memory cells Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes... |
| US-7,684,235 |
Phase change memory A PCRAM cell has a high resistivity bottom electrode cap to provide partial heating near the interface between the cell and the bottom electrode, preventing... |
| US-7,684,228 |
Device and method for using dynamic cell plate sensing in a DRAM memory
cell A memory cell, device, system and method for operating a memory cell utilize an isolated dynamic cell plate. The memory cell includes a first and second pass... |
| US-7,684,227 |
Resistive memory architectures with multiple memory cells per access
device A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is... |
| US-7,683,671 |
Method, apparatus, and system providing power supply independent imager
output driver having a constant slew rate An output driver having an output that is not dependant on the variation of the voltage level of a variable supply voltage. The output driver, having at least... |
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