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| Patent # | Description |
|---|---|
| US-7,644,253 |
Memory hub with internal cache and/or memory access prediction A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory ("SDRAM") devices. The memory hub... |
| US-7,644,240 |
Memory device controller A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core... |
| US-7,644,235 |
Device and method for configuring a cache tag in accordance with burst
length In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not... |
| US-7,643,984 |
Method and system for selecting compatible processors to add to a
multiprocessor computer A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program... |
| US-7,643,370 |
Memory device having conditioning output data Some embodiments of the invention include a memory device having a memory array for storing memory data, a conditioning data storage unit for storing... |
| US-7,643,359 |
Clock generating circuit with multiple modes of operation A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock... |
| US-7,643,343 |
NAND string with a redundant memory cell The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled... |
| US-7,643,333 |
Process for erasing chalcogenide variable resistance memory bits A method of erasing a chalcogenide variable resistance memory cell is provided. The chalcogenide variable resistance memory cell includes a p-doped substrate... |
| US-7,642,827 |
Apparatus and method for multi-phase clock generation An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second... |
| US-7,642,651 |
Multi-layer interconnect with isolation layer An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via,... |
| US-7,642,643 |
Apparatus for molding a semiconductor die package with enhanced thermal
conductivity A method and apparatus for assembling and packaging semiconductor die assemblies utilizes a coating element such as a wafer back side laminate formed on a back... |
| US-7,642,616 |
Tunnel and gate oxide comprising nitrogen for use with a semiconductor
device and a process for forming the device A method used during semiconductor device fabrication comprises forming at least two types of transistors. A first transistor type may comprise a CMOS transistor... |
| US-7,642,591 |
Multi-resistive integrated circuit memory A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a... |
| US-7,642,550 |
Multi-layer structures for parameter measurement Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay... |
| US-7,642,204 |
Methods of forming fluorine doped insulating materials In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing... |
| US-7,642,196 |
Semiconductor fabrication processes Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)... |
| US-7,642,157 |
Method for enhancing electrode surface area in DRAM cell capacitors Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is... |
| US-D607,437 |
Speaker |
| US-7,640,465 |
Memory with element redundancy A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one... |
| US-7,640,413 |
Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit... |
| US-7,639,532 |
Non-equal threshold voltage ranges in MLC NAND Memory devices adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate increases in data... |
| US-7,639,530 |
Method for programming and erasing an NROM cell A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions,... |
| US-7,639,528 |
Nanocrystal write once read only memory for archival storage Structures and methods for write once read only memory employing charge trapping are provided. The write once read only memory cell includes a metal oxide... |
| US-7,639,090 |
Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference... |
| US-7,638,878 |
Devices and systems including the bit lines and bit line contacts A method for forming a semiconductor device comprises forming first and second bit lines at different levels. Forming the bit lines at different levels increases... |
| US-7,638,813 |
Methods of fabrication for flip-chip image sensor packages The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the... |
| US-7,638,436 |
Semiconductor processing methods of transferring patterns from patterned
photoresists to materials The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first... |
| US-7,638,392 |
Methods of forming capacitor structures The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger... |
| US-7,638,357 |
Programmable resistance memory devices and systems using the same and
methods of forming the same A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first... |
| US-7,637,412 |
Apparatus and method for depositing and reflowing solder paste on a
microelectronic workpiece Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and... |
| US-7,636,271 |
User selectable banks for DRAM A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by... |
| US-7,635,991 |
Output buffer strength trimming Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage... |
| US-7,635,630 |
Scalable high density non-volatile memory cells in a contactless memory
array A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion... |
| US-7,635,623 |
Methods of forming capacitors A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising... |
| US-7,635,611 |
Semiconductor substrate for build-up packages The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach... |
| US-7,635,604 |
Well for CMOS imager and method of formation A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically... |
| US-7,635,132 |
Filter cloth connector Apparatuses and methods for making and using a filter cloth assembly are described. A filter cloth assembly can have a liquid permeable filtering medium attached... |
| US-7,635,079 |
System for locating conductive sphere utilizing screen and hopper of
solder balls System for placing conductive spheres on prefluxed bond pads of a substrate using a stencil plate with a pattern of through-holes positioned over the bond pads.... |
| US-7,634,851 |
Method of forming a magnetic random access memory element A method of forming a magnetic tunnel junction memory element and the resulting structure are disclosed. A magnetic tunnel junction memory element comprising a... |
| US-7,634,624 |
Memory system for data storage and retrieval According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system,... |
| US-7,634,623 |
Method and apparatus for self-timed data ordering for multi-data rate
memories and system incorporating same A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during... |
| US-7,634,597 |
Alignment of instructions and replies across multiple devices in a
cascaded system, using buffers of... Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the... |
| US-7,633,821 |
Current mode memory apparatus, systems, and methods Some embodiments include a first circuit to receive input signals and to drive signals at first circuit output nodes, and a second circuit to receive at least a... |
| US-7,633,804 |
Adjusting programming or erase voltage pulses in response to the number of
programming or erase failures Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to... |
| US-7,633,801 |
Memory in logic cell Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate,... |
| US-7,633,798 |
M+N bit programming and M+L bit read for M bit memory cells A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage... |
| US-7,633,786 |
Couplings within memory devices and methods Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer... |
| US-7,633,773 |
On-die anti-resonance structure for integrated circuit A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to... |
| US-7,633,423 |
Method of and apparatus for reducing settling time of a switched capacitor
amplifier A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an... |
| US-7,633,159 |
Semiconductor device assemblies and packages with edge contacts and
sacrificial substrates and other... A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which... |
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