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| Patent # | Description |
|---|---|
| US-7,557,048 |
Methods of forming semiconductor constructions The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can... |
| US-7,557,047 |
Method of forming a layer of material using an atomic layer deposition
process Disclosed is a method of forming a layer of material using an atomic layer deposition (ALD) process in a process chamber of a process tool. In one illustrative... |
| US-7,557,032 |
Silicided recessed silicon Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the... |
| US-7,557,024 |
Single poly CMOS imager More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a... |
| US-7,557,015 |
Methods of forming pluralities of capacitors The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a... |
| US-7,557,013 |
Methods of forming a plurality of capacitors A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises... |
| US-7,557,006 |
Methods of forming field effect transistors A mass of material is formed over a semiconductor substrate. Semiconductive material is formed laterally proximate the mass of material. A space is provided... |
| US-7,557,002 |
Methods of forming transistor devices Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over... |
| US-7,557,001 |
Semiconductor processing methods The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a... |
| US-7,556,897 |
Methods of forming reticles The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes... |
| US-RE40,819 |
Semiconductor device with improved bond pads A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and... |
| US-7,555,358 |
Process and method for continuous, non lot-based integrated circuit
manufacturing A method for continuous, non lot-based manufacturing of integrated circuit (IC) devices of the type to each have a unique fuse identification (ID) includes:... |
| US-7,554,858 |
System and method for reducing pin-count of memory devices, and memory
device testers for same Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output... |
| US-7,554,852 |
Method of erasing flash memory with pre-programming memory cells only in
the presence of a cell leakage Some embodiments include converting a plurality of memory cells into a first logic state, and converting the plurality of memory cells into a second logic state... |
| US-7,554,846 |
Select gate transistors and methods of operating the same Memory arrays, methods and cells are disclosed, such as those involving a floating gate memory array having a plurality of transistors arranged in a plurality of... |
| US-7,554,829 |
Transmission lines for CMOS integrated circuits Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in... |
| US-7,554,589 |
Redundancy in column parallel or row architectures A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row... |
| US-7,554,375 |
Delay line circuit Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are... |
| US-7,554,200 |
Semiconductor devices including porous insulators Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed... |
| US-7,554,171 |
Semiconductor constructions The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and... |
| US-7,554,161 |
HfAlO.sub.3 films for gate dielectrics A dielectric film containing HfAlO.sub.3 and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide... |
| US-7,554,142 |
Ultrashallow photodiode using indium The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to... |
| US-7,554,071 |
Method and apparatus providing pixel array having automatic light control
pixels and image capture pixels A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC)... |
| US-7,553,770 |
Reverse masking profile improvements in high aspect ratio etch A method of improving high aspect ratio etching by reverse masking to provide a more uniform mask height between the array and periphery is presented. A layer of... |
| US-7,553,735 |
Scalable high performance non-volatile memory cells using multi-mechanism
carrier transport A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate... |
| US-7,553,699 |
Method of fabricating microelectronic devices Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality... |
| US-7,553,697 |
Multiple chip semiconductor package A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice,... |
| US-7,553,688 |
Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS... |
| US-7,553,472 |
Nanotube forming methods A nanotube forming method includes growing a plurality of nanotubes to an intermediate length that is deterministic of nanotube intrinsic conductivity.... |
| US-7,552,364 |
Diagnostic and managing distributed processor system A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a... |
| US-7,552,274 |
Flash memory architecture with separate storage of overhead and user data A flash memory system segregates overhead data from user data so that overhead data may be addressed, programmed and erased independently from user data. The... |
| US-7,551,748 |
Earphone The receiver unit includes a receiver body, a housing containing this receiver body, a cord connected to the receiver body, and a cord protector for protecting... |
| US-7,551,510 |
Memory block reallocation in a flash memory device A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability.... |
| US-7,551,509 |
Power circuits for reducing a number of power supply voltage taps required
for sensing a resistive memory A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary... |
| US-7,551,481 |
User configurable commands for flash memory A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of... |
| US-7,551,467 |
Memory device architectures and operation Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines... |
| US-7,551,466 |
Bit line coupling The invention provides methods and apparatus. Alternate bit-line pairs of a memory device are concurrently selected. Each bit-line pair has one bit line formed... |
| US-7,550,985 |
Methods of testing memory devices A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least... |
| US-7,550,848 |
Semiconductor constructions comprising particle-containing materials The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials.... |
| US-7,550,847 |
Packaged microelectronic devices and methods for packaging microelectronic
devices Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ... |
| US-7,550,824 |
Low k interconnect dielectric using surface transformation Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit... |
| US-7,550,818 |
Method of manufacture of a PCRAM memory cell The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having... |
| US-7,550,816 |
Filled trench isolation structure A method for depositing a dielectric in a trench on a semiconductor substrate is provided. The dielectric is deposited by using an HDP-CVD system and performing... |
| US-7,550,762 |
Isolation circuit An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a... |
| US-7,550,380 |
Electroless plating of metal caps for chalcogenide-based memory devices A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first... |
| US-7,550,345 |
Methods of forming hafnium-containing materials The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is... |
| US-7,550,341 |
High density stepped, non-planar flash memory A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same column.... |
| US-7,550,340 |
Silicon rich barrier layers for integrated circuit devices Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to... |
| US-7,550,339 |
Memory device with high dielectric constant gate dielectrics and metal
floating gates A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator... |
| US-7,550,315 |
Method for fabricating semiconductor package with multi-layer die contact
and external contact A semiconductor package includes a substrate formed of a board material, a semiconductor die bonded to the substrate, and an encapsulant on the die. The package... |
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