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| Patent # | Description |
|---|---|
| US-7,544,987 |
High-k dielectric materials and processes for manufacturing them High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition... |
| US-7,544,986 |
System including integrated circuit structures formed in a silicone ladder
polymer layer A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder... |
| US-7,544,984 |
Gettering using voids formed by surface transformation One aspect of this disclosure relates to a memory device, comprising at least one gettering region, a memory array, a plurality of word lines and bit lines, and... |
| US-7,544,921 |
Linear distributed pixel differential amplifier having mirrored inputs A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the... |
| US-7,544,624 |
Systems and methods for processing microfeature workpieces Systems and methods for processing microfeature workpieces are disclosed herein. In one embodiment, the system comprises a processing chamber having a workpiece... |
| US-7,544,622 |
Passivation for cleaning a material A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove... |
| US-7,544,615 |
Systems and methods of forming refractory metal nitride layers using
organic amines A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on... |
| US-7,544,604 |
Tantalum lanthanide oxynitride films Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of... |
| US-7,544,596 |
Atomic layer deposition of GdScO3 films as gate dielectrics The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of gadolinium oxide (Gd.sub.2O.sub.3) and scandium oxide (Sc.sub.2O.sub.3) acting as a... |
| US-7,544,592 |
Method for increasing etch rate during deep silicon dry etch A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of... |
| US-7,544,584 |
Localized compressive strained semiconductor One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline... |
| US-7,544,563 |
Methods of forming a plurality of capacitors The invention includes methods and integrated circuitry. Pillars project outwardly from openings in a first material over individual capacitor storage node... |
| US-7,544,559 |
Methods of forming semiconductor constructions The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material... |
| US-7,544,554 |
Methods of forming gatelines and transistor devices The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for... |
| US-7,544,506 |
System and method for heating, cooling and heat cycling on microfluidic
device An integrated heat exchange system on a microfluidic card. According to one aspect of the invention, the portable microfluidic card has a heating, cooling and... |
| US-7,544,388 |
Methods of depositing materials over substrates, and methods of forming
layers over substrates The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is... |
| US-7,542,614 |
Image feature identification and motion compensation apparatus, systems,
and methods Apparatus, systems, and methods disclosed herein may estimate the magnitude of relative motion between a scene and an image capture device used to capture the... |
| US-7,542,336 |
Architecture and method for NAND flash memory A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are... |
| US-7,542,319 |
Chalcogenide glass constant current device, and its method of fabrication
and operation The invention is related to methods and apparatus for providing a two-terminal constant current device, and its operation thereof. The invention provides a... |
| US-7,542,129 |
Patterning apparatuses and methods for the same An apparatus for patterning a workpiece may include at least two spatial light modulators. The at least two spatial light modulators may receive and relay... |
| US-7,541,963 |
Variable quantization ADC for image sensors An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system,... |
| US-7,541,871 |
Operational transconductance amplifier (OTA) Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include... |
| US-7,541,851 |
Control of a variable delay line using line entry point to modify line
power supply voltage Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input... |
| US-7,541,825 |
Isolation circuit The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first... |
| US-7,541,658 |
Optically interactive device package array An image sensor package and methods for simultaneously fabricating a plurality of such packages. A layer of barrier material comprising a matrix of raised walls... |
| US-7,541,648 |
Electrostatic discharge (ESD) protection circuit An electrostatic discharge (ESD) protection circuit that includes a parallel connection of parasitic vertical and lateral bipolar junction transistors (BJTs)... |
| US-7,541,635 |
Semiconductor fabrication using a collar In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first... |
| US-7,541,632 |
Relaxed-pitch method of aligning active area to digit line According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at... |
| US-7,541,270 |
Methods for forming openings in doped silicon dioxide Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma... |
| US-7,541,242 |
NROM memory cell, memory array, related devices and methods An array of memory cells configured to store at least one bit per one F.sup.2 includes substantially vertical structures providing an electronic memory function... |
| US-7,541,081 |
Phase change memory for archival data storage A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a... |
| US-7,540,018 |
Data security for digital data storage A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be... |
| US-7,539,921 |
Parity bit system for a CAM A CAM includes a parity bit system for error detection. In one embodiment, in each CAM cell, the data portion has its own data parity bit while the status... |
| US-7,539,896 |
Repairable block redundancy scheme A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection when... |
| US-7,539,062 |
Interleaved memory program and verify method, device and system An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells. The... |
| US-7,539,052 |
Non-volatile multilevel memory cell programming Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number... |
| US-7,539,048 |
Method and apparatus processing variable resistance memory cell write
operation A circuit and method for writing to a variable resistance memory cell. The circuit includes a variable resistance memory cell, a switchable current blocking... |
| US-7,538,880 |
Turbidity monitoring methods, apparatuses, and sensors Semiconductor processors, sensors, semiconductor processing systems, semiconductor workpiece processing methods, and turbidity monitoring methods are provided.... |
| US-7,538,858 |
Photolithographic systems and methods for producing
sub-diffraction-limited features Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit.... |
| US-7,538,801 |
Region-based auto gain control and auto exposure control method and
apparatus An apparatus and method for performing automatic exposure and gain control while minimizing oscillations as well as providing a good response time, for example,... |
| US-7,538,702 |
Quantizing circuits with variable parameters Systems, methods, and devices, such as a device including a floating-gate transistor, a quantizing circuit coupled to the floating-gate transistor, and a... |
| US-7,538,590 |
Methods and apparatus for dividing a clock signal There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true... |
| US-7,538,572 |
Off-chip driver apparatus, systems, and methods Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis... |
| US-7,538,413 |
Semiconductor components having through interconnects A semiconductor component includes a semiconductor substrate having a substrate contact on a circuit side thereof in electrical communication with an integrated... |
| US-7,538,392 |
Pseudo SOI substrate and associated semiconductor devices The present invention is generally directed to a method of forming a pseudo SOI substrate and semiconductor devices. In one illustrative embodiment, the method... |
| US-7,538,389 |
Capacitorless DRAM on bulk silicon A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of... |
| US-7,538,372 |
Twin p-well CMOS imager A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in... |
| US-7,538,036 |
Methods of forming openings, and methods of forming container capacitors A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer.... |
| US-7,538,028 |
Barrier layer, IC via, and IC line forming methods A barrier layer forming method includes providing a porous dielectric layer over a substrate, the dielectric layer having a surface with exposed pores, and... |
| US-7,538,001 |
Transistor gate forming methods and integrated circuits A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal... |
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