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Patent # Description
US-7,511,644 Variable resistance logic
A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new...
US-7,511,534 Circuits, devices, systems, and methods of operation for a linear output driver
Embodiments are described for an output driver circuit capable of maintaining a substantially constant output impedance across a wide range of output voltages....
US-7,511,531 Temperature-compensated output buffer
A temperature-compensated output buffer circuit is disclosed, which includes a pull-up circuit including a first pull-up transistor for providing a first pull-up...
US-7,511,520 Universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,511,364 Floating lead finger on a lead frame, lead frame strip, and lead frame assembly including same
A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame...
US-7,511,363 Copper interconnect
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,511,356 Voltage-controlled semiconductor inductor and method
A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor...
US-7,511,354 Well for CMOS imager and method of formation
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically...
US-7,511,341 SOI device having increased reliability and reduced free floating body effects
The present invention provides a novel method for increasing the amount of deuterium incorporated into trap sites of a transistor device during a deuterium...
US-7,511,326 ALD of amorphous lanthanide doped TiO.sub.x films
The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO.sub.x) doped with lanthanide elements, such as samarium,...
US-7,511,262 Optical device and assembly for use with imaging dies, and wafer-label imager assembly
Microelectronic imagers with integrated optical devices and methods for manufacturing imagers. The imagers, for example, typically have an imaging unit including...
US-7,510,983 Iridium/zirconium oxide structure
Embodiments of an electronic apparatus and embodiments for methods of forming the electronic apparatus include a conductive layer having an iridium-based layer,...
US-7,510,966 Electrically conductive line, method of forming an electrically conductive line, and method of reducing...
The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration...
US-7,510,961 Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure
A method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed...
US-7,510,954 Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access...
US-7,510,897 Photodiode with self-aligned implants for high quantum efficiency and method of formation
A pinned photodiode with a pinned surface layer formed by a self-aligned angled implant is disclosed. The angle of the implant may be tailored to provide an...
US-7,509,543 Circuit and method for error test, recordation, and repair
In a memory device, an on-die register is provided that is configured to store a row address as well as a column address of a memory cell that fails a test....
US-7,509,474 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-7,509,005 Resistive heater for thermo optic device
Resistive heaters formed in two mask counts on a surface of a grating of a thermo optic device thereby eliminating one mask count from prior art manufacturing...
US-7,508,722 Memory device having strobe terminals with multiple functions
A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device...
US-7,508,708 NAND string with a redundant memory cell
The invention provides methods and apparatus. A NAND memory block has a source select line for selectively coupling one or more strings of series-coupled...
US-7,508,648 Atomic layer deposition of Dy doped HfO.sub.2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a...
US-7,508,075 Self-aligned poly-metal structures
A semiconductor structure is provided comprising a self-aligned poly-metal stack formed over a semiconductor substrate where the interface between an oxidation...
US-7,508,074 Etch stop layer in poly-metal structures
In accordance with one embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor...
US-7,508,025 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,508,024 Three dimensional flash cell
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to...
US-7,508,016 CMOS imager having on-chip ROM
A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other...
US-7,507,672 Plasma etching system and method
A system and a process for plasma etching a semiconductor device. The technique comprises periodically applying a heightened voltage bias during the plasma...
US-7,506,226 System and method for more efficiently using error correction codes to facilitate memory device testing
A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of...
US-7,506,146 Fast and compact circuit for bus inversion
A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog...
US-7,506,126 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit...
US-7,505,357 Column/row redundancy architecture using latches programmed from a look up table
A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when...
US-7,505,341 Low voltage sense amplifier and sensing method
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the...
US-7,505,330 Phase-change random access memory employing read before write for resistance stabilization
An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase...
US-7,505,323 Programming memory devices
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether...
US-7,505,317 Method, apparatus, and system for providing initial state random access memory
A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for...
US-7,505,309 Static RAM memory cell with DNR chalcogenide devices and method of forming
An SRAM memory device having improved stability including two series connected devices, at least one of the devices being a chalcogenide device exhibiting...
US-7,504,843 Probe unit substrate
A ceramic substrate has, on its surface, a multilayer wiring division, on which micro cantilever type probes are fixed. The multilayer wiring division has the...
US-7,504,767 Electrode structures, display devices containing the same
An electrode structure for a display device comprising a gate electrode proximate to an emitter and a focusing electrode separated from the gate electrode by an...
US-7,504,730 Memory elements
Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and...
US-7,504,687 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,504,685 Oxide epitaxial isolation
Non-volatile memory cell structures are described that are formed by a method including forming a first oxide layer on a horizontal strained substrate, forming...
US-7,504,674 Electronic apparatus having a core conductive structure within an insulating layer
Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a...
US-7,504,310 Semiconductors bonded on glass substrates
A method includes providing a glass substrate and bonding a semiconductor layer to the glass substrate. The semiconductor layer is formed to a thickness such...
US-7,504,298 Method for forming memory cell and device
A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to...
US-7,504,285 Carrierless chip package for integrated circuit devices, and methods of making same
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an...
US-7,504,284 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic...
US-7,503,046 Method of obtaining interleave interval for two data values
A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2.sup.z-n may be used...
US-7,503,002 Text based markup language resource interface
A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference...
US-7,502,659 Sorting a group of integrated circuit devices for those devices requiring special testing
A method for sorting integrated circuit (IC) devices of the type having a fuse identification (ID) into those devices requiring enhanced reliability testing and...
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