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Patent # Description
US-7,466,600 System and method for initiating a bad block disable process in a non-volatile memory
A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid...
US-7,465,999 Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,465,983 Low tunnel barrier insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,465,982 Capacitor structures
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,465,650 Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry
This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of...
US-7,465,627 Methods of forming capacitors
This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first...
US-7,465,616 Method of forming a field effect transistor
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,465,608 Three-dimensional multichip module
A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted...
US-7,465,607 Methods of fabrication of lead frame-based semiconductor device packages incorporating at least one land grid...
Methods of fabrication of lead frame-based semiconductor device packages including at least one land grid array package. At least one semiconductor die is...
US-7,465,488 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,465,406 Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface...
In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The...
US-7,464,308 CAM expected address search testmode
A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected...
US-7,464,231 Method for self-timed data ordering for multi-data rate memories
A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during...
US-7,463,542 Temperature sensing device in an integrated circuit
A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature...
US-7,463,520 Memory device with variable trim settings
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one...
US-7,463,367 Estimating overlay error and optical aberrations
Aberration marks, which may be used in conjunction with lenses in optical photolithography systems, may assist in estimating overlay errors and optical...
US-7,463,099 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,463,052 Method and circuit for off chip driver control, and memory device using same
An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is...
US-7,462,935 Structure and method for forming a capacitively coupled chip-to-chip signaling interface
A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first...
US-7,462,559 Systems and methods for forming metal-containing layers using vapor deposition processes
A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use...
US-7,462,534 Methods of forming memory circuitry
The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a...
US-7,462,510 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,462,088 Method for making large-area FED apparatus
A method is provided for forming and associating a lower section of a large-area field emission device ("FED") that is sealed under a predetermined level of...
US-7,461,320 Memory system and method having selective ECC during low power refresh
A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM...
US-7,461,306 Output data compression scheme using tri-state
A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or...
US-7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous...
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from...
US-7,461,188 Capacitive multidrop bus compensation
The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes...
US-7,461,139 Network computer providing mass storage, broadband access, and other enhanced functionality
A network computer system includes a processor and a memory device coupled to the processor. The memory device contains an embedded operating system that is...
US-7,460,432 Sequential access memory with system and method
A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality...
US-7,460,430 Memory devices having reduced coupling noise between wordlines
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that...
US-7,460,429 Circuit and method for reducing power in a memory device during standby modes
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit...
US-7,460,398 Programming a memory with varying bits per cell
Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates...
US-7,459,944 Low current wide VREF range input buffer
A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing...
US-7,459,930 Digital calibration circuits, devices and systems including same, and methods of operation
A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a...
US-7,459,923 Probe interposers and methods of fabricating probe interposers
The invention includes probe interposers and methods of fabricating pose interposers. In one implementation, a method of fabricating a probe interposer includes...
US-7,459,797 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,459,778 Chip on board leadframe for semiconductor components having area array
A leadframe for semiconductor components includes leadfingers, interconnect bonding sites for wire bonding to a semiconductor die, terminal bonding sites for...
US-7,459,773 Stackable ball grid array
A memory package having a plurality of vertically stacked ball grid arrays. Each of the vertically stacked ball grid arrays has a memory chip coupled thereto....
US-7,459,764 Method of manufacture of a PCRAM memory cell
The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having...
US-7,459,757 Transistor structures
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
US-7,459,746 Method of forming inside rough and outside smooth HSG electrodes and capacitor structure
A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a...
US-7,459,742 Method of manufacturing sidewall spacers on a memory device, and device comprising same
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall...
US-7,459,740 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,459,739 Double density MRAM with planar processing
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-7,459,668 Method, apparatus, and system to reduce ground resistance in a pixel array
Methods, devices, and systems for an image sensor device are disclosed. An image sensor device comprises an array of image pixels wherein each pixel is...
US-7,459,638 Absorbing boundary for a multi-layer circuit board structure
The invention comprises an improved PCB board design having particular utility for high frequency application, and especially useful to alleviate the problem of...
US-7,459,393 Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias...
A method for fabricating a semiconductor component includes the steps of providing a substrate having a contact on a circuit side thereof, forming an opening...
US-7,459,363 Line edge roughness reduction
A method for reducing line edge roughness comprises forming a masking structure on a substrate assembly, wherein the substrate assembly includes a number of...
US-7,459,362 Methods of forming DRAM arrays
The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double...
US-7,459,346 Intrinsic thermal enhancement for FBGA package
A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the...
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