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Patent # Description
US-7,502,058 Imager with tuned color filter
An optimized color filter array is formed in, above or below a one or more damascene layers. The color filter array includes filter regions which are configured...
US-7,501,971 Analog-to-digital converter with resistor ratio
Various embodiments disclose apparatus, systems, and methods operating with a first circuit branch with transistors coupled in series between first and second...
US-7,501,963 Balanced data bus inversion
A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the "balance" of data...
US-7,501,691 Trench insulation structures including an oxide liner and oxidation barrier
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a...
US-7,501,684 Methods of forming semiconductor constructions
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-7,501,676 High density semiconductor memory
A memory cell, array and device include cross-shaped active areas and polysilicon gate areas disposed over arm portions of adjacent cross-shaped active areas....
US-7,501,672 Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a...
A method used to form a semiconductor device provides a silicide layer on a plurality of transistor word lines and on a plurality of conductive plugs. In one...
US-7,501,329 Wafer gettering using relaxed silicon germanium epitaxial proximity layers
One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a...
US-7,501,313 Method of making semiconductor BGA package having a segmented voltage plane
A semiconductor device assembly and method of making the device are disclosed. The assembly comprises a semiconductor die attached to an electrically conductive...
US-7,501,309 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,500,858 Portable electronic device with built-in terminal cover structure
A portable electronic device including a housing having a receptacle for at least one semiconductor die, a terminal carried by the housing and operably coupled...
US-7,500,731 Printer and print control method
In a printer, an MPU makes a flash ROM store a temperature read by a temperature sensor at the time of setting of a correction value and a misalignment...
US-7,499,983 Web dispatch service
A system and method for accessing an application server includes sending a service command from a requestor to a dispatch server, processing the service command...
US-7,499,362 Techniques for storing accurate operating current values
A technique for storing accurate operating current values using programmable elements on memory devices. More specifically, programmable elements, such as...
US-7,499,330 Programming method for NAND EEPROM
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by...
US-7,499,329 Flash memory array using adjacent bit line as source
A memory array having a plurality of flash memory cells arranged in rows and columns. A plurality of bit lines couple the columns such that alternate bit lines...
US-7,499,302 Noise reduction in a CAM memory cell
A dynamic CAM cell has features that reduce the effect of noise within a CAM array. By shielding the matchline from the wordline, noise transmitted from the...
US-7,498,875 Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers
The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and...
US-7,498,759 Semiconductor wafer processing accelerometer
An end effector of a robot tool that includes accelerometers and methods to sense end effector motion. A semiconductor substrate or similar object may be...
US-7,498,675 Semiconductor component having plate, stacked dice and conductive vias
A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an...
US-7,498,670 Semiconductor structures having electrophoretically insulated vias
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,498,647 Packaged microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in...
US-7,498,629 Stud electrode and process for making same
A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process...
US-7,498,606 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,498,265 Epitaxial silicon growth
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon...
US-7,498,260 Pass through via technology for use during the manufacture of a semiconductor device
A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of...
US-7,498,258 Through-hole conductors for semiconductor substrates and method for making same
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
US-7,498,247 Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,498,240 Microfeature workpieces, carriers, and associated methods
Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can...
US-7,498,231 Multiple data state memory cell
A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a...
US-7,498,230 Magnesium-doped zinc oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain...
US-7,498,057 Deposition methods
A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls...
US-7,497,958 Methods of forming capacitors
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which...
US-7,497,825 Data download to imager chip using image sensor as a receptor
An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to...
US-7,497,005 Method for forming an inductor
A method of fabricating an inductor includes selecting a substrate, depositing a layer of magnetic material on the substrate, depositing an insulating layer on...
US-7,496,235 Scan line to block re-ordering buffer for image compression
A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing...
US-7,495,966 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,495,964 Method and apparatus for sensing flash memory using delta sigma modulation
A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a...
US-7,495,487 Delay-locked loop (DLL) system for determining forward clock path delay
A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line...
US-7,495,316 Methods of forming conductive vias and methods of forming multichip modules including such conductive vias
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,495,277 Memory circuitry
The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors....
US-7,494,939 Methods for forming a lanthanum-metal oxide dielectric layer
Atomic layer deposited lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of...
US-7,494,925 Method for making through-hole conductors for semiconductor substrates
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
US-7,494,922 Small electrode for phase change memories
A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is...
US-7,494,910 Methods of forming semiconductor package
The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon...
US-7,494,894 Protection in integrated circuits
A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a...
US-7,494,889 Method of manufacturing an interposer including at least one passive element at least partially defined by a...
An interposer for assembly with a semiconductor die and methods of manufacture are disclosed. The interposer may include at least one passive element at least...
US-7,494,873 Memory utilizing oxide-nitride nanolaminates
Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain...
US-7,494,750 Reticles
The invention includes reticles and methods of forming reticles. In one aspect, a reticle can include a quartz-containing substrate, an attenuating layer, and an...
US-7,493,442 Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index...
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