Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,444,550 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,444,537 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,444,458 Method for assigning addresses to memory devices
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an...
US-7,444,030 Image encoding with dynamic buffer-capacity-level-based compression adjustment
Methods, systems, and computer programs for encoding images are described. In one aspect, quantized frequency domain vectors are sequentially generated from a...
US-7,443,761 Loop filtering for fast PLL locking
Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL)...
US-7,443,750 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor...
US-7,443,749 Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor...
US-7,443,743 Method and system for improved efficiency of synchronous mirror delays and delay locked loops
A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and...
US-7,443,715 SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell...
US-7,443,437 Image sensor with a gated storage node linked to transfer gate
A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer...
US-7,443,427 Wide dynamic range linear-and-log active pixel
A pixel circuit having an improved dynamic range is disclosed. When incoming light detected by the photodiode is strong, the accumulated (integrated) charge on a...
US-7,443,219 Phase interpolation apparatus, systems, and methods
A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal...
US-7,443,216 Trimmable delay locked loop circuitry with improved initialization characteristics
Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay...
US-7,443,038 Flip-chip image sensor packages
The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the...
US-7,443,032 Memory device with chemical vapor deposition of titanium for titanium silicide contacts
A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor...
US-7,443,022 Board-on-chip packages
The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A ...
US-7,443,009 N well implants to separate blocks in a flash memory device
A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is...
US-7,443,006 Photon amplification of image sensors
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer...
US-7,442,979 Reduced cell-to-cell shorting for memory arrays
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell...
US-7,442,977 Gated field effect devices
This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device...
US-7,442,976 DRAM cells with vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-7,442,970 Active photosensitive structure with buried depletion layer
An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a...
US-7,442,910 High dynamic range cascaded integration pixel cell
A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a...
US-7,442,655 Selective oxidation methods and transistor fabrication methods
The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a...
US-7,442,643 Methods of forming conductive elements using organometallic layers and flowable, curable conductive materials
A conductive element is formed on a substrate by forming an organometallic layer on at least a portion of a surface of the substrate, heating a portion of the...
US-7,442,633 Decoupling capacitor for high frequency noise immunity
Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the...
US-7,442,608 Methods of fabricating a semiconductor device using angled implantation
Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a...
US-7,442,600 Methods of forming threshold voltage implant regions
The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger...
US-7,442,578 Underfill compounds including electrically charged filler elements, microelectronic devices having underfill...
Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler...
US-7,442,472 Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-7,442,319 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,441,949 System and method for providing temperature data from a memory device having a temperature sensor
A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature...
US-7,441,172 DVI link with parallel test data
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random...
US-7,440,860 Sequential unique marking
The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices...
US-7,440,344 Level shifter for low voltage operation
A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply...
US-7,440,339 Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading...
US-7,440,336 Memory device having terminals for transferring multiple types of data
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,440,332 Low power multiple bit sense amplifier
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers...
US-7,440,321 Multiple select gate architecture with select gates of different lengths
A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the...
US-7,440,317 One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
US-7,440,310 Memory cell with trenched gated thyristor
One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of...
US-7,440,255 Capacitor constructions and methods of forming
A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor...
US-7,440,012 Method and apparatus for optimizing image sensor noise and dynamic range
A method and apparatus for optimizing the voltage supply of an image sensor pixel array to minimize pixel noise and maximize dynamic range is disclosed. The...
US-7,439,752 Methods of providing semiconductor components within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,439,598 Microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,439,594 Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a...
US-7,439,576 Ultra-thin body vertical tunneling transistor
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on...
US-7,439,564 Methods of forming capacitor constructions
The invention includes constructions having two dielectric layers over a conductively-doped semiconductive material. One of the dielectric layers contains...
US-7,439,479 Photonic crystal-based filter for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal filter into an image sensor. The photonic crystal filter comprises a substrate...
US-7,439,450 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.