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Patent # Description
US-7,498,265 Epitaxial silicon growth
Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon...
US-7,498,260 Pass through via technology for use during the manufacture of a semiconductor device
A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of...
US-7,498,258 Through-hole conductors for semiconductor substrates and method for making same
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
US-7,498,247 Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,498,240 Microfeature workpieces, carriers, and associated methods
Microfeature workpieces, carriers, and associated methods are disclosed. In a particular embodiment, one method for processing a microfeature workpiece can...
US-7,498,231 Multiple data state memory cell
A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a...
US-7,498,230 Magnesium-doped zinc oxide structures and methods
Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain...
US-7,498,057 Deposition methods
A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls...
US-7,497,958 Methods of forming capacitors
The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which...
US-7,497,825 Data download to imager chip using image sensor as a receptor
An imaging device having a CMOS photosensor array for capturing images is described in which the array is also used to input programming and/or data used to...
US-7,497,005 Method for forming an inductor
A method of fabricating an inductor includes selecting a substrate, depositing a layer of magnetic material on the substrate, depositing an insulating layer on...
US-7,496,235 Scan line to block re-ordering buffer for image compression
A re-order buffer memory in a real-time application such as e.g., an imager. Initially, input data is written into the re-order buffer using a first addressing...
US-7,495,966 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,495,964 Method and apparatus for sensing flash memory using delta sigma modulation
A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a...
US-7,495,487 Delay-locked loop (DLL) system for determining forward clock path delay
A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line...
US-7,495,316 Methods of forming conductive vias and methods of forming multichip modules including such conductive vias
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,495,277 Memory circuitry
The invention includes memory circuitry. In one implementation, memory circuitry includes a memory array comprising a plurality of memory cell capacitors....
US-7,494,939 Methods for forming a lanthanum-metal oxide dielectric layer
Atomic layer deposited lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of...
US-7,494,925 Method for making through-hole conductors for semiconductor substrates
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
US-7,494,922 Small electrode for phase change memories
A method of manufacturing a memory cell is disclosed. In one embodiment, the method includes forming an electrode including an outer surface that is...
US-7,494,910 Methods of forming semiconductor package
The invention includes semiconductor packages having grooves within a semiconductor die backside; and includes semiconductor packages utilizing carbon...
US-7,494,894 Protection in integrated circuits
A method including, prior to a plasma heat-up operation, forming a liner on a structure coated with an insulator. And a method including forming a trench on a...
US-7,494,889 Method of manufacturing an interposer including at least one passive element at least partially defined by a...
An interposer for assembly with a semiconductor die and methods of manufacture are disclosed. The interposer may include at least one passive element at least...
US-7,494,873 Memory utilizing oxide-nitride nanolaminates
Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain...
US-7,494,750 Reticles
The invention includes reticles and methods of forming reticles. In one aspect, a reticle can include a quartz-containing substrate, an attenuating layer, and an...
US-7,493,442 Multiple segment data object management
A multiple segment data structure and method manage data objects stored in multiple segments. The structure and method use one or more multiple segment index...
US-7,492,652 Apparatus and method for repairing a semiconductor memory
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit...
US-7,492,376 Graphics resampling system and method for use thereof
A resampling circuit and method where input sample values for samples arranged along a row of a source image are received by a row resampling circuit. The row...
US-7,492,287 Two-bit tri-level forced transition encoding
An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every...
US-7,492,196 Low injection charge pump
A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are...
US-7,492,086 Low work function emitters and method for production of FED's
According to one aspect of the invention, a field emission display is provided comprising: an anode; a phosphor screen located on the anode; a cathode; an...
US-7,492,042 Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
US-7,492,039 Assemblies and multi-chip modules including stacked semiconductor dice having centrally located, wire bonded...
An assembly method that includes providing a first semiconductor device and positioning a second semiconductor device at least partially over the first...
US-7,492,030 Techniques to create low K ILD forming voids between metal lines
One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer...
US-7,492,027 Reduced crosstalk sensor and method of formation
Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating...
US-7,491,995 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-7,491,963 Non-volatile memory structure
A non-volatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead...
US-7,491,962 Resistance variable memory device with nanoparticle electrode and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a...
US-7,491,650 Etch compositions and methods of processing a substrate
The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH.sub.4F and tetramethyl ammonium fluoride (TMAF). The...
US-7,491,641 Method of forming a conductive line and a method of forming a conductive contact adjacent to and insulated from...
This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a...
US-7,491,636 Methods for forming flexible column die interconnects and resulting structures
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal...
US-7,491,608 Vertical transistor with horizontal gate layers
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable...
US-7,491,602 Structures and methods for improved capacitor cells in integrated circuits
Systems, devices, structures, and methods are described that inhibit atomic migration that creates an open contact between a metallization layer and a conductive...
US-7,491,570 Die package having an adhesive flow restriction area
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element....
US-7,490,211 Memory hub with integrated non-volatile memory
A memory hub having an integrated non-volatile memory for storing configuration information is provided. The memory hub includes a high-speed interface for...
US-7,490,210 System and method for processor with predictive memory retrieval assist
A system and method are described for a memory management processor which, using a table of reference addresses embedded in the object code, can open the...
US-7,490,190 Method and system for local memory addressing in single instruction, multiple data computer system
A single instruction, multiple data ("SIMD") computer system includes a central control unit coupled to 256 processing elements ("PEs") and to 32 static random...
US-7,489,875 System and method for multiple bit optical data transmission in memory systems
The disclosed system and method data increases data transmission speed through a memory system by using optical signals comprising a plurality of wavelengths of...
US-7,489,587 Semiconductor memory device capable of controlling clock cycle time for reduced power consumption
Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first...
US-7,489,575 Noise resistant small signal sensing circuit for a memory device
Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus...
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