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Patent # Description
US-7,488,618 Microlenses including a plurality of mutually adhered layers of optically transmissive material and systems...
Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material....
US-7,488,514 Methods of forming barium strontium titanate layers
A chemical vapor deposition method of forming a barium strontium titanate comprising dielectric layer. A substrate is positioned within a reactor. Barium and...
US-7,488,386 Atomic layer deposition methods and chemical vapor deposition methods
The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave...
US-7,486,550 Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating...
US-7,486,530 Method of comparison between cache and data register for non-volatile memory
A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer...
US-7,485,971 Electronic device package
An electronic device package is described that includes a non-metal die attached adhesive. The die attach is positioned in discrete positions on a surface to...
US-7,485,969 Stacked microelectronic devices and methods for manufacturing microelectronic devices
Stacked microelectronic devices and methods for manufacturing such devices. An embodiment of a microelectronic device can include a support member and a first...
US-7,485,961 Approach to avoid buckling in BPSG by using an intermediate barrier layer
A method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The present method involves...
US-7,485,948 Front-end processing of nickel plated bond pads
A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an...
US-7,485,942 Films deposited at glancing incidence for multilevel metallization
Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit...
US-7,485,904 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,485,836 Row driver for selectively supplying operating power to imager pixel
An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout...
US-7,485,587 Method of making a semiconductor device having improved contacts
A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In...
US-7,485,565 Nickel bonding cap over copper metalized bondpads
A method for forming a nickel cap layer over copper metalized bond pad is disclosed in which the phosphorous content of the nickel cap, and particularly the...
US-7,485,562 Method of making multichip wafer level packages and computing systems incorporating same
The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and...
US-7,485,548 Die loss estimation using universal in-line metric (UILM)
A system predicts die loss for a semiconductor wafer by using a method referred to as universal in-line metric (UILM). A wafer inspection tool detects defects on...
US-7,485,544 Strained semiconductor, devices and systems and methods of formation
In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The...
US-7,485,528 Method of forming memory devices by performing halogen ion implantation and diffusion processes
Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes...
US-7,485,526 Floating-gate structure with dielectric component
Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within...
US-7,485,513 One-device non-volatile random access memory cell
One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a...
US-7,485,504 Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an...
US-7,485,497 Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
US-7,484,142 System and method for testing a memory for a memory failure exhibited by a failing memory
A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a...
US-7,483,334 Interleaved input signal path for multiplexed input
System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment,...
US-7,483,333 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,483,330 Power efficient memory and cards
A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a...
US-7,483,315 Techniques for implementing accurate operating current values stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
US-7,483,311 Erase operation in a flash memory device
A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the...
US-7,483,305 Method, apparatus and system relating to automatic cell threshold voltage measurement
Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current...
US-7,483,286 Semiconductor memory device with high permeability lines interposed between adjacent transmission lines
A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
US-7,483,067 Column-parallel sigma-delta analog-to-digital conversion for imagers
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that do not rely on the ratio of the reset and pixel voltage levels...
US-7,482,855 Circuit and method for stable fuse detection
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal...
US-7,482,833 Method and circuit for controlling pin capacitance in an electronic device
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively...
US-7,482,798 Regulated internal power supply and method
A regulated internal power supply and method are provided. According to various embodiments, a regulated internal power supply system includes a DC to DC...
US-7,482,702 Semiconductor component sealed on five sides by polymer sealing layer
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,482,687 Etch stop in a damascene interconnect structure
An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials...
US-7,482,653 Non-volatile memory with carbon nanotubes
Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into...
US-7,482,651 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or...
US-7,482,630 NAND memory arrays
A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate...
US-7,482,284 Deposition methods for forming silicon oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-7,482,239 Methods of forming integrated circuitry
In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor...
US-7,482,229 DRAM cells with vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-7,482,190 Micromechanical strained semiconductor by wafer bonding
One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are...
US-7,482,176 Etch mask and method of forming a magnetic random access memory structure
A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering...
US-7,482,037 Methods for forming niobium and/or vanadium containing layers using atomic layer deposition
A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a...
US-7,481,887 Apparatus for controlling gas pulsing in processes for depositing materials onto micro-device workpieces
An apparatus for depositing materials onto a micro-device workpiece includes a gas source system configured to provide a first precursor, a second precursor, and...
US-7,480,792 Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing...
Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance....
US-7,480,762 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,480,203 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,480,202 High speed array pipeline architecture
A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into...
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