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Patent # Description
US-7,470,563 Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such...
A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection...
US-7,470,552 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,470,344 Chemical dispensing system for semiconductor wafer processing
A method for dispensing a chemical, such as an edge bead removal solvent, onto a semiconductor wafer comprising the steps of dispensing the chemical selectively...
US-D583,856 Ink ribbon cassette
US-7,468,922 Apparatus and method for dynamically repairing a semiconductor memory
An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing...
US-7,468,623 Clamp circuit with fuse options
A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage...
US-7,468,610 Electrical connecting apparatus
An electrical connecting apparatus comprising: a circuit board on which a reinforcing plate is mounted and a plurality of first electric connections are...
US-7,468,559 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,468,534 Localized masking for semiconductor structure development
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical...
US-7,468,533 Terraced film stack
A process and apparatus directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present...
US-7,468,323 Method of forming high aspect ratio structures
An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure...
US-7,468,108 Metal layer forming methods and capacitor electrode forming methods
A capacitor electrode forming method includes chemisorbing a layer of at least one metal precursor at least one monolayer thick on a substrate, the layer...
US-7,468,105 CMP cleaning composition with microbial inhibitor
An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are...
US-7,468,104 Chemical vapor deposition apparatus and deposition method
A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by at least one of a chamber sidewall and a chamber base wall. A...
US-7,467,334 Method for repairing a semiconductor memory
A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row....
US-7,466,618 Current limiting antifuse programming path
Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the...
US-7,466,615 Low voltage data path and current sense amplifier
Methods, circuits, devices, and systems are provided, including a low voltage data path and current sense amplifier. One data path includes a local input/output...
US-7,466,606 Memory device having terminals for transferring multiple types of data
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,466,602 Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
US-7,466,600 System and method for initiating a bad block disable process in a non-volatile memory
A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid...
US-7,465,999 Fully-depleted (FD) (SOI) MOSFET access transistor
A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity...
US-7,465,983 Low tunnel barrier insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,465,982 Capacitor structures
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,465,650 Methods of forming polysilicon-comprising plugs and methods of forming FLASH memory circuitry
This invention includes methods of forming plugs containing polysilicon, and methods of forming FLASH memory circuitry. In one implementation, a method of...
US-7,465,627 Methods of forming capacitors
This invention includes methods of forming capacitors. In one implementation, a first capacitor electrode material is formed over a substrate. The first...
US-7,465,616 Method of forming a field effect transistor
In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening...
US-7,465,608 Three-dimensional multichip module
A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted...
US-7,465,607 Methods of fabrication of lead frame-based semiconductor device packages incorporating at least one land grid...
Methods of fabrication of lead frame-based semiconductor device packages including at least one land grid array package. At least one semiconductor die is...
US-7,465,488 Bow control in an electronic package
A package including a package substrate, a die-substrate assembly including a substrate including a plurality of layers including a layer having a mesh to...
US-7,465,406 Method of exposing a substrate to a surface microwave plasma, etching method, deposition method, surface...
In certain implementations, methods and apparatus include an antenna assembly having at least two overlapping and movable surface microwave plasma antennas. The...
US-7,464,308 CAM expected address search testmode
A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected...
US-7,464,231 Method for self-timed data ordering for multi-data rate memories
A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during...
US-7,463,542 Temperature sensing device in an integrated circuit
A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature...
US-7,463,520 Memory device with variable trim settings
A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one...
US-7,463,367 Estimating overlay error and optical aberrations
Aberration marks, which may be used in conjunction with lenses in optical photolithography systems, may assist in estimating overlay errors and optical...
US-7,463,099 Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference...
US-7,463,052 Method and circuit for off chip driver control, and memory device using same
An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is...
US-7,462,935 Structure and method for forming a capacitively coupled chip-to-chip signaling interface
A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first...
US-7,462,559 Systems and methods for forming metal-containing layers using vapor deposition processes
A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use...
US-7,462,534 Methods of forming memory circuitry
The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a...
US-7,462,510 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,462,088 Method for making large-area FED apparatus
A method is provided for forming and associating a lower section of a large-area field emission device ("FED") that is sealed under a predetermined level of...
US-7,461,320 Memory system and method having selective ECC during low power refresh
A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM...
US-7,461,306 Output data compression scheme using tri-state
A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or...
US-7,461,286 System and method for using a learning sequence to establish communications on a high-speed nonsynchronous...
A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from...
US-7,461,188 Capacitive multidrop bus compensation
The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes...
US-7,461,139 Network computer providing mass storage, broadband access, and other enhanced functionality
A network computer system includes a processor and a memory device coupled to the processor. The memory device contains an embedded operating system that is...
US-7,460,432 Sequential access memory with system and method
A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality...
US-7,460,430 Memory devices having reduced coupling noise between wordlines
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that...
US-7,460,429 Circuit and method for reducing power in a memory device during standby modes
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit...
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