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Patent # Description
US-7,439,450 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,439,338 Beta-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-7,439,195 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,439,194 Lanthanide doped TiOx dielectric films by plasma oxidation
A dielectric film containing lanthanide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable gate dielectric having an...
US-7,439,169 Integrated circuit and methods of redistributing bondpad locations
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
US-7,439,158 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,439,157 Isolation trenches for memory devices
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the...
US-7,439,155 Isolation techniques for reducing dark current in CMOS image sensors
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an...
US-7,439,152 Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
US-7,439,140 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,439,138 Method of forming integrated circuitry
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one...
US-7,439,136 Method of forming a layer comprising epitaxial silicon
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,438,632 Method and apparatus for cleaning a web-based chemical mechanical planarization system
A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly...
US-7,438,626 Apparatus and method for removing material from microfeature workpieces
Machines and systems for removing materials from microfeature workpieces using fixed-abrasive mediums. One embodiment of a method for removing material from a...
US-7,437,729 Method for load balancing a loop of parallel processing elements
A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing...
US-7,437,726 Method for rounding values for a plurality of parallel processing elements
A method for calculating a local mean number of tasks for each processing element (PE.sub.r) in a parallel processing system, wherein each processing element...
US-7,437,647 Mode entry circuit and method
An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference...
US-7,437,632 Circuits and methods for repairing defects in memory devices
A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the...
US-7,437,630 Testing a multibank memory module
A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of...
US-7,437,625 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,437,579 System and method for selective memory module power management
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the...
US-7,436,708 NAND memory device column charging
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on...
US-7,436,705 Multiple level cell memory device with single bit per cell, re-mappable memory block
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode...
US-7,436,442 Low light sensor signal to noise improvement
A number of different elements are added together in a staggered way to avoid the total loss of resolution caused by the binning process. The circuit for doing...
US-7,436,267 Microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one...
US-7,436,231 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,436,202 Method and apparatus for calibrating driver impedance
The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes...
US-7,436,067 Methods for forming conductive structures and structures regarding same
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal...
US-7,436,020 Flash memory with metal-insulator-metal tunneling program and erase
The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is...
US-7,436,018 Discrete trap non-volatile multi-functional memory device
A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of...
US-7,435,913 Slanted vias for electrical circuits on circuit boards and other substrates
Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting...
US-7,435,688 Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and...
The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first...
US-7,435,641 Low leakage MIM capacitor
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a...
US-7,435,636 Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are...
US-7,435,620 Low temperature methods of forming back side redistribution layers in association with through wafer interconnects
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the...
US-7,435,536 Method to align mask patterns
Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming...
US-7,435,324 Noncontact localized electrochemical deposition of metal thin films
A method of selectively electroplating metal features on a semiconductor substrate having a conductive surface. An electrode assembly that includes a plurality...
US-7,434,152 Multiple-level data compression read mode for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,434,081 System and method for read synchronization of memory modules
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors,...
US-7,433,585 System and method of lens placement
A lens-placement system in accordance with the invention includes an imaging system having an imaging camera to capture an image of at least a portion of an...
US-7,433,250 Sense amplifier circuit
An equalization circuit may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An...
US-7,433,249 Apparatus with equalizing voltage generation circuit and methods of use
A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first...
US-7,433,248 System and method for enhanced mode register definitions
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by...
US-7,433,237 Memory utilizing oxide nanolaminates
One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the...
US-7,433,231 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,433,227 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,432,968 CMOS image sensor with reduced 1/f noise
A CMOS image sensor includes a plurality of pixel circuits. Each pixel circuit includes a plurality of transistors. The image sensor includes a controller for...
US-7,432,774 Microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one...
US-7,432,604 Semiconductor component and system having thinned, encapsulated dice
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,432,600 System having semiconductor component with multiple stacked dice
A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking...
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