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SRAM devices, and electronic systems comprising SRAM devices
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
Silicon lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of...
Apparatus having a memory device with floating gate layer grain boundaries
with oxidized portions
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an...
Dual conversion gain gate and capacitor combination
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective...
Pixel with spatially varying sensor positions
An image sensor including a substrate, at least one metal layer, and a plurality of pixels arranged in array. Each pixel includes a sense element disposed in the...
Compositions for dissolution of low-k dielectric film, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
Methods of processing a semiconductor substrate
The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface....
Methods of patterning photoresist, and methods of forming semiconductor
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between...
Methods of forming a nitrogen enriched region
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
Methods of forming HSG layers and devices
A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas...
Shallow trench isolation by atomic-level silicon reconstruction
Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to...
Isolation process and structure for CMOS imagers
A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical...
Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
Atomic layer deposition method of depositing an oxide on a substrate
The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a...
Atomic layer deposition apparatus and method
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first deposition precursor is fed...
Methods of operating a liquid vaporizer
The present invention is generally directed to a vaporizer with positive liquid shut-off. In one illustrative embodiment, the vaporizer is comprised of a body, a...
Method for load balancing a line of parallel processing elements
A method for balancing the load of a parallel processing system having parallel processing elements (PEs) linked serially in a line with first and second ends,...
Digital imaging system and method for adjusting image-capturing parameters
using image comparisons
A digital imaging system and method for manually adjusting the image-capturing parameters of a digital imaging device of the system utilizes a comparative image...
High performance multi-level non-volatile memory device
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping...
Memory with strained semiconductor by wafer bonding with misorientation
One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding...
Method of forming trench isolation in the fabrication of integrated
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
Use of a plasma source to form a layer during the formation of a
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
Use of selective oxidation to form asymmetrical oxide features during the
manufacture of a semiconductor device
A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The...
Microelectronic imagers with optical devices having integral reference
features and methods for manufacturing...
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed...
Line width error check
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum...
Memory controller method and system compensating for memory cell data
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
Apparatus and methods for testing memory devices
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test...
System and method for selective memory module power management
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the...
Delivery of solid chemical precursors
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor, pressure sensor, or...
Phase detector and method providing rapid locking of delay-lock loops
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals...
Semiconductor device with self refresh test mode
A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or...
Low power NROM memory devices
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion...
Gapless microlens array and method of fabrication
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a...
Resilient contact probe apparatus
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different...
Rear plate for plasma display panel with barrier ribs having specific
Disclosed is a rear plate of a plasma display panel. In the rear plate, barrier ribs are formed by etching a baked barrier rib layer, so that the completed...
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a...
Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
Sacrificial self-aligned interconnect structure
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and...
Memory array for increased bit density
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
Pixel with differential readout
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a...
Method and apparatus for providing a rolling double reset timing for
global storage in image sensors
An apparatus for and a method of operating an array of pixels of an image sensor, where each pixel includes at least a photosensor, an associated storage device...
Method and apparatus for setting black level in an imager using both
optically black and tied pixels
An imaging pixel array includes an active area of pixels, organized into rows and columns of pixels. The array also includes a plurality of dark pixel columns...
Porous organosilicate layers, and vapor deposition systems and methods for
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
High density stepped, non-planar nitride read only memory
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge...
Semiconductor/printed circuit board assembly, and computer system
A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate...
Passivated magneto-resistive bit structure and passivation method therefor
A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure...
Reactors with isolated gas connectors and methods for depositing materials
onto micro-device workpieces
Reactors having gas distributors for depositing materials onto micro-device workpieces, systems that include such reactors, and methods for depositing materials...