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Patent # Description
US-7,483,333 Memory device and method having banks of different sizes
A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of...
US-7,483,330 Power efficient memory and cards
A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a...
US-7,483,315 Techniques for implementing accurate operating current values stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
US-7,483,311 Erase operation in a flash memory device
A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the...
US-7,483,305 Method, apparatus and system relating to automatic cell threshold voltage measurement
Methods and apparatuses for automatically measuring memory cell threshold voltages are disclosed. Measurement circuitry includes an internal reference current...
US-7,483,286 Semiconductor memory device with high permeability lines interposed between adjacent transmission lines
A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
US-7,483,067 Column-parallel sigma-delta analog-to-digital conversion for imagers
A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that do not rely on the ratio of the reset and pixel voltage levels...
US-7,482,855 Circuit and method for stable fuse detection
A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal...
US-7,482,833 Method and circuit for controlling pin capacitance in an electronic device
A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively...
US-7,482,798 Regulated internal power supply and method
A regulated internal power supply and method are provided. According to various embodiments, a regulated internal power supply system includes a DC to DC...
US-7,482,702 Semiconductor component sealed on five sides by polymer sealing layer
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,482,687 Etch stop in a damascene interconnect structure
An interconnect structure with a plurality of low dielectric constant insulating layers acting as etch stops is disclosed. The low dielectric constant materials...
US-7,482,653 Non-volatile memory with carbon nanotubes
Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into...
US-7,482,651 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or...
US-7,482,630 NAND memory arrays
A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate...
US-7,482,284 Deposition methods for forming silicon oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-7,482,239 Methods of forming integrated circuitry
In one implementation, an opening within a capacitor electrode forming layer is formed over a substrate. A spacing layer is deposited over the capacitor...
US-7,482,229 DRAM cells with vertical transistors
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain...
US-7,482,190 Micromechanical strained semiconductor by wafer bonding
One aspect disclosed herein relates to a method for forming a strained semiconductor structure. In various embodiments of the method, a number of recesses are...
US-7,482,176 Etch mask and method of forming a magnetic random access memory structure
A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering...
US-7,482,037 Methods for forming niobium and/or vanadium containing layers using atomic layer deposition
A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a...
US-7,481,887 Apparatus for controlling gas pulsing in processes for depositing materials onto micro-device workpieces
An apparatus for depositing materials onto a micro-device workpiece includes a gas source system configured to provide a first precursor, a second precursor, and...
US-7,480,792 Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing...
Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance....
US-7,480,762 Erase block data splitting
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data...
US-7,480,203 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,480,202 High speed array pipeline architecture
A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into...
US-7,480,199 Method for low power refresh of a dynamic random access memory using a slower refresh rate than a normal...
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data...
US-7,480,195 Internal data comparison for memory testing
Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data...
US-7,480,186 NROM flash memory with self-aligned structural charge separation
A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride...
US-7,480,185 Ballistic injection NROM flash memory
A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by...
US-7,480,098 Microlens array sheet having black matrix and method of manufacturing the same
Disclosed herein are a microlens array sheet having a black matrix and a method for manufacturing the same. The manufacturing method includes a) the step of...
US-7,479,650 Method of manufacture of programmable conductor memory
Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom...
US-7,479,440 Method of forming an isolation structure that includes forming a silicon layer at a base of the recess
A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a...
US-7,479,413 Method for fabricating semiconductor package with circuit side polymer layer
A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a...
US-7,479,206 Apparatus for in-situ optical endpointing on web-format planarizing machines in mechanical or...
Polishing pads, planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies. The...
US-RE40,623 Method and apparatus for identifying integrated circuits
An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic...
US-7,478,032 Method and system for selecting compatible processors to add to a multiprocessor computer
A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program...
US-7,477,570 Sequential access memory with system and method
A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality...
US-7,477,557 256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array...
US-7,477,556 256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array...
US-7,477,554 Data retention kill function
A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and...
US-7,477,542 Split gate flash memory cell with ballistic injection
A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of...
US-7,477,306 Method and apparatus for improving pixel output swing in imager sensors
A bias readout circuit is disclosed for use in reading out a pixel of an imager system. The bias readout circuit includes a circuit portion which mirrors an...
US-7,477,304 Two narrow band and one wide band color filter for increasing color image sensor sensitivity
A color filter to increase the low light sensitivity of an image sensor. The color filter has two narrow band color filters and one wide band filter. Also...
US-7,477,298 Anti-eclipsing circuit for image sensors
An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection...
US-7,476,955 Die package having an adhesive flow restriction area
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element....
US-7,476,933 Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
US-7,476,927 Scalable multi-functional and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two...
US-7,476,925 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,476,861 Passenger detection apparatus
A passenger detection device that determines whether a passenger sits in a passenger seat or backseat, and if YES, determines whether the passenger is an adult...
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