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Patent # Description
US-7,427,425 Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
Reactors having gas distributors for depositing materials onto micro-device workpieces, systems that include such reactors, and methods for depositing materials...
US-7,426,148 Method and apparatus for identifying short circuits in an integrated circuit device
The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of...
US-7,425,847 Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
US-7,425,839 Systems and methods for testing packaged microelectronic devices
Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a...
US-7,425,758 Metal core foldover package structures
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked ...
US-7,425,742 NAND flash cell structure
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating...
US-7,425,507 Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an...
US-7,425,499 Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed...
US-7,425,491 Nanowire transistor with surrounding gate
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous...
US-7,425,472 Semiconductor fuses and semiconductor devices containing the same
A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link...
US-7,425,470 Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,425,463 Stacked die package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,425,462 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities...
US-7,425,461 Photon amplification for image sensors
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer...
US-7,424,635 System and method for power saving delay locked loop control by selectively locking delay interval
The delay locked loop ("DLL") delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL...
US-7,424,634 System and method for reducing jitter of signals coupled through adjacent signal lines
A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects...
US-7,424,629 Data controlled power supply apparatus
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
US-7,424,593 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash...
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed....
US-7,424,581 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-7,424,557 System for determining status of multiple interlocking FIFO buffer structures based on the position of at least...
One embodiment of the present invention relates to a method for using at least two first-in, first-out ("FIFO") buffers in a pipelined bus, comprising,...
US-7,424,330 Method and apparatus for controlling deformable actuators
In order to prevent negative effects of imprinting an the addressing accuracy of deformable actuators, a method for controlling deformable actuators has, during...
US-7,424,082 Digital lock detector for PLL
Circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit are provided. A frequency divider outputs a clock having a frequency...
US-7,423,923 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the...
US-7,423,922 Defective block handling in a flash memory device
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines...
US-7,423,919 Method and system for improved efficiency of synchronous mirror delays and delay locked loops
A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and...
US-7,423,918 Memory device having data paths with multiple speeds
A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of...
US-7,423,676 Asymmetric comparator for use in pixel oversaturation detection
An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are...
US-7,423,476 Current mirror circuit having drain-source voltage clamp
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output...
US-7,423,465 Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction...
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal....
US-7,423,463 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,423,462 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,423,456 Fast response time, low power phase detector circuits, devices and systems incorporating the same, and...
A circuit for quickly accomplishing highly accurate phase detection using low power is described. The circuit includes a phase decision circuit that receives two...
US-7,423,345 Semiconductor constructions comprising a layer of metal over a substrate
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid....
US-7,423,338 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,423,336 Bond pad rerouting element, rerouted semiconductor devices including the rerouting element, and assemblies...
A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The...
US-7,423,331 Molded stiffener for thin substrates
A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is...
US-7,423,311 Atomic layer deposition of Zr.sub.3N.sub.4/ZrO.sub.2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr.sub.3N.sub.4) and zirconium oxide (ZrO.sub.2) and a method of...
US-7,423,249 Layout technique for address signal lines in decoders including stitched blocks
A decoder block includes a number of generic blocks stitched together. The generic blocks have an address line layout that enables the decoders to be addressed...
US-7,422,986 Deposition methods utilizing microwave excitation
The invention includes a deposition apparatus having a reaction chamber, and a microwave source external to the chamber. The microwave source is configured to...
US-7,422,978 Methods of manufacturing interposers with flexible solder pad elements
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-7,422,966 Technique for passivation of germanium
A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide layer. The...
US-7,422,960 Method of forming gate arrays on a partial SOI substrate
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to...
US-7,422,948 Threshold voltage adjustment for long channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-7,422,927 Methods of forming a resistance variable element
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one...
US-7,422,924 Image device and photodiode structure
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first...
US-7,422,639 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
US-7,422,635 Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature...
The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One...
US-RE40,490 Method and apparatus for programmable field emission display
A method and apparatus for programmable field emission display comprising an array of cathodoluminescent elements. Each cathodoluminescent element in the array...
US-7,421,630 Apparatus and methods for testing memory devices
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test...
US-7,421,607 Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data...
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