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Patent # Description
US-7,422,978 Methods of manufacturing interposers with flexible solder pad elements
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-7,422,966 Technique for passivation of germanium
A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide layer. The...
US-7,422,960 Method of forming gate arrays on a partial SOI substrate
The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to...
US-7,422,948 Threshold voltage adjustment for long channel transistors
A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor...
US-7,422,927 Methods of forming a resistance variable element
The invention includes methods of depositing silver onto a metal selenide-comprising surface, and methods of forming a resistance variable device. In one...
US-7,422,924 Image device and photodiode structure
The invention provides a photodiode with an increased charge collection area, laterally spaced from an adjacent isolation region. Dopant ions of a first...
US-7,422,639 Method of reducing water spotting and oxide growth on a semiconductor structure
The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.
US-7,422,635 Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature...
The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One...
US-RE40,490 Method and apparatus for programmable field emission display
A method and apparatus for programmable field emission display comprising an array of cathodoluminescent elements. Each cathodoluminescent element in the array...
US-7,421,630 Apparatus and methods for testing memory devices
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test...
US-7,421,607 Method and apparatus for providing symmetrical output data for a double data rate DRAM
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data...
US-7,421,606 DLL phase detection using advanced phase equalization
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL)....
US-7,421,121 Spectral normalization using illuminant exposure estimation
After image capture, scene parameters are analyzed, e.g. lux, flicker, or world estimation. A best guess illuminant for the scene parameters is determined. At...
US-7,420,849 Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
US-7,420,361 Method for improving stability and lock time for synchronous circuits
Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay...
US-7,420,240 Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner...
An exposed top end of a vertical oxide spacer is removed, and a nitride layer is deposited in an amount sufficient to replace the removed portion prior to...
US-7,420,239 Dielectric layer forming method and devices formed therewith
Embodiments in accordance with the present invention provide alternative materials, and methods of forming such materials, that are effective as dielectric...
US-7,420,238 Semiconductor constructions
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,420,233 Photodiode for improved transfer gate leakage
An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by...
US-7,420,154 Pixel circuit with non-destructive readout circuit and methods of operation thereof
A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image...
US-7,419,913 Methods of forming openings into dielectric material
This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material,...
US-7,419,895 NAND memory arrays
Methods and apparatus are provided. A source slot and a drain contact region are formed at opposite ends of a NAND string disposed on a substrate of a NAND...
US-7,419,871 Methods of forming semiconductor constructions
The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array...
US-7,419,865 Methods of forming memory circuitry
The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node...
US-7,419,854 Methods for packaging image sensitive electronic devices
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS...
US-7,419,852 Low temperature methods of forming back side redistribution layers in association with through wafer...
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the...
US-7,419,841 Microelectronic imagers and methods of packaging microelectronic imagers
Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a...
US-7,419,768 Methods of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a...
US-7,419,638 Microfluidic devices for fluid manipulation and analysis
The present invention relates to microfluidic devices and methods for manipulating and analyzing fluid samples. The disclosed microfluidic devices utilize a...
US-7,419,299 Methods of sensing temperature of an electronic device workpiece
The present invention includes electronic device workpieces, methods of semiconductor processing and methods of sensing temperature of an electronic device...
US-7,418,526 Memory hub and method for providing memory sequencing hints
A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller...
US-7,418,161 Photonic crystal-based optical elements for integrated circuits and methods therefor
Exemplary embodiments of the invention provide photonic crystal-based optical elements for integrated circuits. A photonic crystal optical device comprises a...
US-7,418,071 Method and apparatus for generating a phase dependent control signal
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector...
US-7,417,916 Methods of reducing coupling noise between wordlines
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that...
US-7,417,901 Memory device having terminals for transferring multiple types of data
A memory device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,417,894 Single latch data circuit in a multiple level cell non-volatile memory device
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a...
US-7,417,893 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,417,677 Lag cancellation in CMOS image sensors
A pixel cell with improved lag characteristics without increased noise. The pixel cell according to embodiments of the invention includes a photo-conversion...
US-7,417,674 Multi-magnification color image sensor
A color image sensor has imaging elements each structured to form, at an image plane, an image of a subject having a respective magnification. Ones of the...
US-7,417,505 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,417,478 Delay line circuit
Methods, circuits, devices, and systems are provided, including a delay line for a delay-locked loop. One method includes providing a reference clock to a first...
US-7,417,325 Semiconductor component having thinned die with conductive vias configured as conductive pin terminal contacts
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,417,305 Electronic devices at the wafer level having front side and edge protection material and systems including the...
Methods for applying a dielectric protective layer to a wafer in wafer-level chip scale package manufacture are disclosed. A flowable dielectric protective...
US-7,417,294 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Microelectronic imaging units and methods for manufacturing microelectronic imaging units are disclosed herein. In one embodiment, a method includes placing a...
US-7,417,280 Method and apparatus for a flash memory device comprising a source local interconnect
A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a...
US-7,417,272 Image sensor with improved dynamic range and method of formation
Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor...
US-7,416,994 Atomic layer deposition systems and methods including metal beta-diketiminate compounds
The present invention provides atomic layer deposition systems and methods that include metal compounds with at least one .beta.-diketiminate ligand. Such...
US-7,416,958 Epitaxial semiconductor layer and method
A method for epitaxially forming a first semiconductor structure attached to a second semiconductor structure is provided. Devices and methods described include...
US-7,416,943 Peripheral gate stacks and recessed array gates
Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic...
US-7,416,933 Methods of enabling polysilicon gate electrodes for high-k gate dielectrics
Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors are formed with an...
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