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Patent # Description
US-7,442,578 Underfill compounds including electrically charged filler elements, microelectronic devices having underfill...
Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler...
US-7,442,472 Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-7,442,319 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,441,949 System and method for providing temperature data from a memory device having a temperature sensor
A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature...
US-7,441,172 DVI link with parallel test data
An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random...
US-7,440,860 Sequential unique marking
The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices...
US-7,440,344 Level shifter for low voltage operation
A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply...
US-7,440,339 Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading...
US-7,440,336 Memory device having terminals for transferring multiple types of data
A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary...
US-7,440,332 Low power multiple bit sense amplifier
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers...
US-7,440,321 Multiple select gate architecture with select gates of different lengths
A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the...
US-7,440,317 One transistor SOI non-volatile random access memory cell
One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various...
US-7,440,310 Memory cell with trenched gated thyristor
One aspect of this disclosure relates to a method for operating a memory cell. According to various embodiments, the method includes charging a storage node of...
US-7,440,255 Capacitor constructions and methods of forming
A capacitor construction includes a first electrode and a layer between the first electrode and a surface supporting the capacitor construction. The capacitor...
US-7,440,012 Method and apparatus for optimizing image sensor noise and dynamic range
A method and apparatus for optimizing the voltage supply of an image sensor pixel array to minimize pixel noise and maximize dynamic range is disclosed. The...
US-7,439,752 Methods of providing semiconductor components within sockets
The invention includes methods of utilizing removable mechanical precising mechanisms and/or optical-based precising mechanisms to align chips within sockets....
US-7,439,598 Microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,439,594 Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a...
US-7,439,576 Ultra-thin body vertical tunneling transistor
A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on...
US-7,439,564 Methods of forming capacitor constructions
The invention includes constructions having two dielectric layers over a conductively-doped semiconductive material. One of the dielectric layers contains...
US-7,439,479 Photonic crystal-based filter for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal filter into an image sensor. The photonic crystal filter comprises a substrate...
US-7,439,450 Plating buss and a method of use thereof
The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly,...
US-7,439,338 Beta-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-7,439,195 Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,439,194 Lanthanide doped TiOx dielectric films by plasma oxidation
A dielectric film containing lanthanide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable gate dielectric having an...
US-7,439,169 Integrated circuit and methods of redistributing bondpad locations
Integrated circuits and methods of redistributing bondpad locations are disclosed. In one implementation, a method of redistributing a bondpad location of an...
US-7,439,158 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,439,157 Isolation trenches for memory devices
A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the...
US-7,439,155 Isolation techniques for reducing dark current in CMOS image sensors
Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an...
US-7,439,152 Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
US-7,439,140 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,439,138 Method of forming integrated circuitry
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one...
US-7,439,136 Method of forming a layer comprising epitaxial silicon
The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of...
US-7,438,632 Method and apparatus for cleaning a web-based chemical mechanical planarization system
A method and apparatus for cleaning a web-based chemical-mechanical planarization (CMP) system. Specifically, a fluid spray bar is coupled to a frame assembly...
US-7,438,626 Apparatus and method for removing material from microfeature workpieces
Machines and systems for removing materials from microfeature workpieces using fixed-abrasive mediums. One embodiment of a method for removing material from a...
US-7,437,729 Method for load balancing a loop of parallel processing elements
A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, wherein each processing...
US-7,437,726 Method for rounding values for a plurality of parallel processing elements
A method for calculating a local mean number of tasks for each processing element (PE.sub.r) in a parallel processing system, wherein each processing element...
US-7,437,647 Mode entry circuit and method
An apparatus and method for generating an active mode activation signal in response to an input signal having a voltage exceeding the greater of two reference...
US-7,437,632 Circuits and methods for repairing defects in memory devices
A memory device has a number of memory segments connected to a supply source through a supply control circuit. If one of the memory segments is defective, the...
US-7,437,630 Testing a multibank memory module
A method and system for testing a memory module that has at least a first and second memory bank. The first and second memory banks have a plurality of...
US-7,437,625 Memory with element redundancy
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one...
US-7,437,579 System and method for selective memory module power management
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the...
US-7,436,708 NAND memory device column charging
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on...
US-7,436,705 Multiple level cell memory device with single bit per cell, re-mappable memory block
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode...
US-7,436,442 Low light sensor signal to noise improvement
A number of different elements are added together in a staggered way to avoid the total loss of resolution caused by the binning process. The circuit for doing...
US-7,436,267 Microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one...
US-7,436,231 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,436,202 Method and apparatus for calibrating driver impedance
The present invention provides a method and apparatus is provided for calibrating a driver impedance in an integrated circuit device. The method includes...
US-7,436,067 Methods for forming conductive structures and structures regarding same
A method for forming a metal/metal oxide structure that includes forming metal oxide regions, e.g., ruthenium oxide regions, at grain boundaries of a metal...
US-7,436,020 Flash memory with metal-insulator-metal tunneling program and erase
The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is...
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