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Patent # Description
US-9,406,880 Resistive memory having confined filament formation
Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon...
US-9,406,878 Resistive memory cells with two discrete layers of programmable material, methods of programming memory cells,...
Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across...
US-9,406,874 Magnetic memory cells and methods of formation
Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress...
US-9,406,660 Stacked semiconductor die assemblies with die support members and associated systems and methods
Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,406,623 Electromagnetic shield and associated methods
Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material,...
US-9,406,606 Semiconductor device having a reduced area and enhanced yield
A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power...
US-9,406,404 Column redundancy system for a memory array
A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to...
US-9,406,389 Electronically coupling a data line to a source for biasing regardless of states of memory cells coupled to the...
Memory devices and methods are disclosed, such as those facilitating data line shielding by way of capacitive coupling with data lines coupled to a memory...
US-9,406,388 Memory area protection system and methods
In one embodiment, a non-volatile memory device includes a plurality of protection bits denoting that an area of memory in the device must be protected from...
US-9,406,384 Matching semiconductor circuits
Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between...
US-9,406,363 Memory apparatus and system with shared wordline decoder
A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels,...
US-9,406,362 Memory tile access and selection patterns
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile...
US-9,406,357 Data capture system and method, and memory controllers and devices
Embodiments of a data capture system and method may be used in a variety of devices, such as in memory controllers and memory devices. The data capture system...
US-9,406,353 Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell
Sense amplifiers, memories, and apparatuses and methods for sensing a data state of a memory cell are disclosed. An example apparatus includes a differential...
US-9,405,874 Time-domain signal generation
Methods and apparatuses disclose various embodiments of time-domain signal generation. In one embodiment a method includes receiving an input waveform having a...
US-9,405,859 Using do not care data with feature vectors
Methods for storing a feature vector, as well as related comparison units and systems. One such method involves programming a string of memory cells of memory...
US-9,405,721 Apparatuses and methods for performing a databus inversion operation
Apparatuses and methods for performing a data bus inversion operation (DBI) are described. An example apparatus includes a DBI circuit configured to, in...
US-9,405,679 Determining a location of a memory device in a solid state device
A solid state device has a controller. The controller is configured to perform a first division operation that divides a received logical block address that...
US-9,405,676 Devices and methods for operating a solid state drive
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired...
US-9,405,639 Systems and methods for retrieving data
Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques...
US-9,405,622 Shaping codes for memory
Apparatuses and methods associated with shaping codes for memory are provided. One example apparatus comprises an array of memory cells and a shaping component...
US-9,405,475 Multi-interface memory with access control
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels...
US-9,405,355 Memory operation power management by data transfer time adjustment
The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an...
US-9,401,745 Wireless communication link using near field coupling
A memory device may include an array of closely spaced memory integrated circuits that communicate wirelessly over at least two frequencies using near field...
US-9,401,476 Methods of forming memory structures
Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes,...
US-9,401,474 Methods of forming structures
Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along...
US-9,401,363 Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices
A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the...
US-9,401,285 Chemical mechanical planarization topography control via implant
Systems and methods for chemical mechanical planarization topography control via implants are disclosed. In one embodiment, a method of manufacturing a...
US-9,401,188 Devices and systems including enabling circuits
Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices,...
US-9,400,755 Password accessible microelectronic memory
A microelectronic memory may be password access protected. A controller may maintain a register with requirements for accessing particular memory locations to...
US-9,400,707 Error detection or correction of stored signals after one or more heat events in one or more memory devices
The present disclosure includes methods, devices, and systems for error detection or correction of stored signals in memory devices. An example method includes...
US-9,400,705 Hardwired remapped memory
Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.
US-9,400,309 Electric connecting apparatus
An apparatus includes a probe card having a probe board with a conductive path electrically connected to a tester and probes enabling to respectively contact...
US-9,397,290 Memory cells
Memory cells useful in phase change memory include a phase change material between first and second electrode and having a surface facing a surface of the...
US-9,397,210 Forming air gaps in memory arrays and memory arrays with air gaps thus formed
A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an...
US-9,397,187 Methods of forming diodes
Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is...
US-9,397,145 Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory...
A memory structure comprises first conductive lines extending in a first direction over portions of a base structure, storage element structures extending in...
US-9,397,105 Nanodot charge storage structures
Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of...
US-9,397,078 Semiconductor device assembly with underfill containment cavity
Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first...
US-9,396,996 Methods of forming openings in semiconductor structures
A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of...
US-9,396,952 Methods of forming transistor gates
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-9,396,791 Programming memories with multi-level pass signal
Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be...
US-9,395,927 Outputting a particular data quantization from memory
The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting...
US-9,391,645 Determining soft data using a classification code
Apparatuses and methods for determining soft data using a classification code are provided. One example apparatus can include a classification code (CC) decoder...
US-9,391,206 Methods of forming transistors
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with...
US-9,391,092 Circuit structures, memory circuitry, and methods
A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator...
US-9,391,082 Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a...
The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where...
US-9,391,062 Apparatuses, circuits, and methods for protection circuits for dual-direction nodes
Apparatuses, circuits, and methods are disclosed for biased protection circuits for dual-direction nodes. In one such example apparatus, a protection circuit is...
US-9,391,001 Semiconductor constructions
Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection....
US-9,390,882 Apparatus having a magnetic lens configured to diverge an electron beam
Apparatus having a magnetic lens configured to diverge an electron beam are useful in three-dimensional imaging using an electron microscope. The magnetic lens...
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