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Packaged semiconductor components having substantially rigid support
members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
Semiconductor chip covered with sealing resin having a filler material
A semiconductor device includes a wiring substrate, a sealing resin layer formed on the wiring substrate out of a filler-containing resin and having a one-sided...
Methods for forming semiconductor device packages with photoimageable
dielectric adhesive material, and related...
Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and...
Microelectronic devices, stacked microelectronic devices, and methods for
manufacturing such devices
Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly...
Inferring threshold voltage distributions associated with memory cells via
Apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation are described herein. An example includes...
Methods of forming and programming memory devices with isolation
Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a...
Apparatuses including cross point memory arrays and biasing schemes
Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row)...
Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV...
Error protection for memory devices
Subject matter disclosed herein relates to methods and/or apparatuses, such as an apparatus that includes first and second groups of memory cells. The first...
Method and apparatus providing compensation for wavelength drift in
A method and apparatus are described which provide for wavelength drift compensation in a photonic waveguide by application of an electric field to a waveguide...
Substrates and methods of forming a pattern on a substrate
Substrates and methods of forming a pattern on a substrate. The pattern includes a repeating pattern region and a pattern-interrupting region adjacent to the...
Flexible circuit for an implantable neural stimulator
Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same...
Memory cells and methods of fabrication
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The...
Semiconductor devices comprising floating gate transistors and methods of
forming such semiconductor devices
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an...
Semiconductor device structures and arrays of vertical transistor devices
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region...
Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
Charge trapping dielectric structures
A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator...
Method providing an epitaxial growth having a reduction in defects and
Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size...
Vertical devices and methods of forming
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor...
Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
Interconnect structure with redundant electrical connectors and associated
systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
Build-up package for integrated circuit devices, and methods of making
A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a...
Land grid array semiconductor device packages
A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the...
Method and apparatus providing integrated circuit having redistribution
layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
Semiconductor device with an overlay mark including segment regions
surrounded by a pool region
Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a...
Methods of forming semiconductor structures
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
Methods of forming and using materials containing silicon and nitrogen
Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer...
Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G...
Metallization scheme for integrated circuit
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level...
Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
Searching using multilevel cells and programming multilevel cells for
Methods of searching and methods of programming a memory are provided. In one such method of searching, a determination is made as to whether an attribute of a...
Signal driver circuit having adjustable output voltage for a high logic
level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
Horizontally oriented and vertically stacked memory cells
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first...
Memory cells, semiconductor devices, and methods of fabrication
A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic...
Semiconductor graphene structures, semiconductor devices including such
structures, and related methods
A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material,...
Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
Semiconductor die assemblies with heat sink and associated systems and
Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a...
Isolation trench fill using oxide liner and nitride etch back technique
with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
Repair of memory devices using volatile and non-volatile memory
Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The...
Apparatuses and methods for limiting string current in a memory
Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string...
Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,...
Applying substantially the same voltage differences across memory cells at
different locations along an access...
An embodiment of a method of programming might include applying a first voltage difference across a first memory cell to be programmed, where applying the first...
Programming memory cells using smaller step voltages for higher program
Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first...
Memory devices and memory operational methods including single erase
operation of conductive bridge memory cells
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with...
Select devices for memory cell applications
Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more non-ohmic select devices can...
Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells are disclosed. One method embodiment includes storing charges corresponding to a data state...
Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
Apparatuses and methods for comparing a current representative of a number
of failing memory cells
Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current...
Flexible and expandable memory architectures
Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a...