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Patent # Description
US-9,389,833 Method and system to dynamically power-down a block of a pattern-recognition processor
A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of...
US-9,385,317 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,385,315 Memory cell structures
The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled...
US-9,385,278 Semiconductor growth substrates and associated systems and methods for die singulation
Semiconductor growth substrates and associated systems and methods for die singulation are disclosed. A representative method for manufacturing semiconductor...
US-9,385,276 Epitaxial devices
Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice...
US-9,385,132 Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of...
A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask...
US-9,385,112 Semiconductor devices
A semiconductor device includes a substrate having laterally-adjacent first and second substrate regions. A first isolation region is at least in the first...
US-9,385,045 Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
US-9,384,830 Apparatuses and methods for performing multiple memory operations
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory...
US-9,384,814 Thyristor memory and methods of operation
Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is...
US-9,384,799 Advanced memory interfaces and methods
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and...
US-9,384,785 Multi-channel memory and power supply-driven channel selection
Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels...
US-9,384,134 Persistent memory for processor main memory
Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
US-9,384,127 Flash memory architecture with separate storage of overhead and user data
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A...
US-9,379,315 Memory cells, methods of fabrication, semiconductor device structures, and memory systems
Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one...
US-9,379,241 Semiconductor device with strained channels
In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region...
US-9,379,199 Semiconductor device including a contact plug with barrier materials
Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a...
US-9,379,091 Semiconductor die assemblies and semiconductor devices including same
Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice...
US-9,379,005 Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the...
US-9,378,847 Systems and methods involving managing a problematic memory cell
Subject matter described pertains to managing problematic memory cells in a memory array.
US-9,378,839 Apparatus and methods including source gates
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor...
US-9,378,823 Programming a memory cell to a voltage to indicate a data value and after a relaxation time programming the...
A memory cell is programmed to at least a first threshold voltage to indicate a particular data value. After waiting for a relaxation time, the memory cell is...
US-9,378,818 Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines
The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data...
US-9,378,791 Apparatuses and methods for controlling a clock signal provided to a clock tree
Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command...
US-9,378,790 Apparatus and method for buffered write commands in a memory
Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after...
US-9,378,783 I/O circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state...
US-9,378,774 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
US-9,378,157 Security memory access method and apparatus
Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory...
US-9,374,902 Package including an underfill material in a portion of an area between the package and a substrate or another...
Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having a substrate or a first...
US-9,374,343 Bitwise operations and apparatus in a multi-level system
A system uses multi-level encoding where each symbol of a plurality of symbols represents more than one bit of information in a user data symbol stream for...
US-9,373,779 Magnetic tunnel junctions
A magnetic tunnel junction includes a conductive first magnetic electrode that includes magnetic recording material. A conductive second magnetic electrode is...
US-9,373,775 Methods of forming magnetic memory cells
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods...
US-9,373,716 Impact ionization devices, and methods of forming impact ionization devices
Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of...
US-9,373,715 Semiconductor devices including vertical memory cells and methods of forming same
A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or...
US-9,373,661 Solid state transducer devices, including devices having integrated electrostatic discharge protection, and...
Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment,...
US-9,373,636 Methods of forming semiconductor constructions
Some embodiments include a semiconductor construction having a stack containing alternating levels of control gate material and intervening dielectric material....
US-9,373,404 Sensing memory cells coupled to different access lines in different blocks of memory cells
In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the...
US-9,373,399 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-9,373,392 Memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
US-9,373,377 Apparatuses, integrated circuits, and methods for testmode security systems
Apparatuses, integrated circuits, and methods are disclosed for testmode security systems. In one such example apparatus, a data storage is configured to store...
US-9,373,371 Dynamic burst length output control in a memory
A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by...
US-D759,727 Electric high pressure decompressor
US-9,368,714 Memory cells, methods of operation and fabrication, semiconductor device structures, and memory systems
A magnetic cell core includes at least one stressor structure proximate to a magnetic region (e.g., a free region or a fixed region). The magnetic region may be...
US-9,368,669 Method and apparatus for reducing signal loss in a photo detector
Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect...
US-9,368,581 Integrated circuitry components, switches, and memory cells
A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair....
US-9,368,554 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch...
US-9,368,444 Self-aligned nano-structures
A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer...
US-9,368,216 Interconnections for 3D memory
Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs...
US-9,368,212 Memory with temperature coefficient trimming
A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a...
US-9,368,202 Apparatuses, sense circuits, and methods for compensating for a wordline voltage increase
Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a...
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