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Patent # Description
US-7,452,816 Semiconductor processing method and chemical mechanical polishing methods
This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical...
US-7,452,770 Reduced cell-to-cell shorting for memory arrays
Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell...
US-7,452,766 Finned memory cells and the fabrication thereof
Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality...
US-7,452,760 Thin film transistors and semiconductor constructions
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
US-7,452,759 Carbon nanotube field effect transistor and methods for making same
A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube...
US-7,452,732 Comparing identifying indicia formed using laser marking techniques to an identifying indicia model
A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface...
US-7,451,533 NC automatic lathe
An NC automatic lathe including abase board, a headstock provided with a main spindle and so arranged as to move in a direction of Z1 axis, a back attachment...
US-7,451,343 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,450,465 Read command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,450,462 System and memory for sequential multi-plane page memory operations
A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory...
US-7,450,450 Circuitry for a programmable element
As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse...
US-7,450,447 Memory device and method having low-power, high write latency mode and high-power, low write latency mode...
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low...
US-7,450,425 Non-volatile memory cell read failure reduction
The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment...
US-7,450,422 NAND architecture memory devices and operation
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines...
US-7,450,410 High speed data bus
The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus...
US-7,449,953 Input buffer design using common-mode feedback (CMFB)
An input buffer includes a first stage for receiving an input signal and having a first pair of complementary output signals, the first stage including an input...
US-7,449,941 Master bias current generating circuit with decreased sensitivity to silicon process variation
A master bias current generating circuit includes a current source, a first reference leg, and a second reference leg. The first reference leg includes a first...
US-7,449,939 Bias generator with feedback control
A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage...
US-7,449,910 Test system for semiconductor components having conductive spring contacts
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
US-7,449,906 Probe for testing an electrical device
A probe having a first and a second arm portion extending between first and second connecting portions connecting the first and second arm portions respectively...
US-7,449,766 Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask
Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During...
US-7,449,736 Pixel with transfer gate with no isolation edge
A pixel and imager device, and method of forming the same, where the pixel has a transfer transistor gate associated with a photoconversion device and is...
US-7,449,410 Methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive...
The invention included to methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts. In one...
US-7,449,391 Methods of forming plurality of capacitor devices
The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention...
US-7,449,390 Methods of forming memory
Methods of forming memory are described. According to one arrangement, a method of forming memory includes forming a plurality of word lines over a substrate,...
US-7,449,368 Technique for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over...
US-D580,434 Mobile card reader
US-7,448,038 Method for using filtering to load balance a loop of parallel processing elements
One aspect of the present invention relates to a method for balancing the load of a parallel processing system having a plurality of parallel processing elements...
US-7,447,974 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,447,973 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,447,847 Memory device trims
Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory...
US-7,447,720 Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements
A method for finding an extrema for an n-dimensional array having a plurality of processing elements, the method includes determining within each of the...
US-7,447,327 Flexible PCB voice coil connector
In an electroacoustic transducer, a pair of coil terminals elongating from a voice coil are electrically connected to a pair of terminal members attached to a...
US-7,447,240 Method and system for synchronizing communications links in a hub-based memory system
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs...
US-7,447,106 Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the...
US-7,447,085 Multilevel driver
The present disclosure includes various method, device, and system embodiments for multilevel driving of rowlines and/or wordlines. One such method embodiment...
US-7,446,857 Image forming method and apparatus
An acousto-optic cell is used in a method and device for patterning a workpiece, for exposing a radiation sensitive layer on a workpiece such as a mask or a...
US-7,446,855 Methods and apparatuses for configuring radiation in microlithographic processing of workpieces using an...
Methods and apparatuses for configuring radiation used in microlithographic processing of workpieces are disclosed herein. One particular embodiment of such a...
US-7,446,812 Wide dynamic range operations for imaging
Embodiments provide a method and apparatus that achieve wide dynamic range operation of an image sensor. In an array of pixel cells, first charge is accumulated...
US-7,446,807 Imager pixel with capacitance for boosting reset voltage
A pixel cell in which a capacitance is coupled between a storage node and a row select transistor and another capacitance is coupled between a storage node and a...
US-7,446,610 Low voltage CMOS differential amplifier
A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased...
US-7,446,580 System and method to improve the efficiency of synchronous mirror delays and delay locked loops
A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore...
US-7,446,415 Method for filling electrically different features
Methods of electroless filling electrically different features such as contact openings to form interconnects and conductive contacts, and semiconductor devices,...
US-7,446,393 Co-sputter deposition of metal-doped chalcogenides
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a...
US-7,446,385 Methods of fabricating optical packages, systems comprising the same, and their uses
Methods and apparatuses for forming optical packages, and intermediate structures resulting from the same are disclosed, which provide an optical element over a...
US-7,446,372 DRAM tunneling access transistor
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side...
US-7,446,368 Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,446,363 Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric...
The invention comprises integrated circuitry and to methods of forming capacitors. In one implementation, integrated circuitry includes a capacitor having a...
US-7,446,357 Split trunk pixel layout
A pixel array architecture having multiple pixel cells arranged in a split trunk pixel layout and sharing common pixel cell components. The array architecture...
US-7,446,351 Transistor structures and transistors with a germanium-containing channel
A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel...
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