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Patent # Description
US-7,428,687 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,428,672 Apparatus and methods for testing memory devices
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test...
US-7,428,644 System and method for selective memory module power management
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the...
US-7,428,373 Delivery of solid chemical precursors
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor, pressure sensor, or...
US-7,428,284 Phase detector and method providing rapid locking of delay-lock loops
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals...
US-7,428,181 Semiconductor device with self refresh test mode
A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or...
US-7,428,173 Low power NROM memory devices
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion...
US-7,428,103 Gapless microlens array and method of fabrication
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a...
US-7,427,869 Resilient contact probe apparatus
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different...
US-7,427,837 Rear plate for plasma display panel with barrier ribs having specific width characteristics
Disclosed is a rear plate of a plasma display panel. In the rear plate, barrier ribs are formed by etching a baked barrier rib layer, so that the completed...
US-7,427,811 Semiconductor substrate
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a...
US-7,427,798 Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
US-7,427,793 Sacrificial self-aligned interconnect structure
A sacrificial, self-aligned polysilicon interconnect structure is formed in a region of insulating material to the side of an active region location and...
US-7,427,770 Memory array for increased bit density
A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode,...
US-7,427,737 Pixel with differential readout
An imager in which two adjacent pixels share row and reset lines and a row selection circuitry while the output transistors of the two pixels are configured as a...
US-7,427,736 Method and apparatus for providing a rolling double reset timing for global storage in image sensors
An apparatus for and a method of operating an array of pixels of an image sensor, where each pixel includes at least a photosensor, an associated storage device...
US-7,427,735 Method and apparatus for setting black level in an imager using both optically black and tied pixels
An imaging pixel array includes an active area of pixels, organized into rows and columns of pixels. The array also includes a plurality of dark pixel columns...
US-7,427,570 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
US-7,427,536 High density stepped, non-planar nitride read only memory
A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge...
US-7,427,535 Semiconductor/printed circuit board assembly, and computer system
A method of forming a computer system and a printed circuit board assembly, are provided comprising first and second semiconductor dies and an intermediate...
US-7,427,514 Passivated magneto-resistive bit structure and passivation method therefor
A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure...
US-7,427,425 Reactors with isolated gas connectors and methods for depositing materials onto micro-device workpieces
Reactors having gas distributors for depositing materials onto micro-device workpieces, systems that include such reactors, and methods for depositing materials...
US-7,426,148 Method and apparatus for identifying short circuits in an integrated circuit device
The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of...
US-7,425,847 Input buffer with optimal biasing and method thereof
A method and circuit of a biased input buffer is described to maximize the quality in the output signals. The input buffer includes a first stage for receiving...
US-7,425,839 Systems and methods for testing packaged microelectronic devices
Systems and methods for testing packaged microelectronic devices are disclosed herein. One such system for testing a packaged microelectronic device includes a...
US-7,425,758 Metal core foldover package structures
Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked ...
US-7,425,742 NAND flash cell structure
NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize continuous channel enhancement and depletion mode floating...
US-7,425,507 Semiconductor substrates including vias of nonuniform cross section, methods of forming and associated structures
Methods for forming a via and a conductive path are disclosed. The methods include forming a via within a wafer with cyclic etch/polymer phases, followed by an...
US-7,425,499 Methods for forming interconnects in vias and microelectronic workpieces including such interconnects
Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed...
US-7,425,491 Nanowire transistor with surrounding gate
One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous...
US-7,425,472 Semiconductor fuses and semiconductor devices containing the same
A fuse for use in a semiconductor device includes spaced-apart terminals with at least two layers of conductive material and a single-layer conductive link...
US-7,425,470 Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,425,463 Stacked die package for peripheral and center device pad layout device
An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least...
US-7,425,462 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing
Methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities...
US-7,425,461 Photon amplification for image sensors
A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer...
US-7,424,635 System and method for power saving delay locked loop control by selectively locking delay interval
The delay locked loop ("DLL") delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL...
US-7,424,634 System and method for reducing jitter of signals coupled through adjacent signal lines
A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects...
US-7,424,629 Data controlled power supply apparatus
A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a...
US-7,424,593 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash...
In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed....
US-7,424,581 Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory...
US-7,424,557 System for determining status of multiple interlocking FIFO buffer structures based on the position of at least...
One embodiment of the present invention relates to a method for using at least two first-in, first-out ("FIFO") buffers in a pipelined bus, comprising,...
US-7,424,330 Method and apparatus for controlling deformable actuators
In order to prevent negative effects of imprinting an the addressing accuracy of deformable actuators, a method for controlling deformable actuators has, during...
US-7,424,082 Digital lock detector for PLL
Circuits and methods for detecting a lock condition of a phase-locked loop (PLL) circuit are provided. A frequency divider outputs a clock having a frequency...
US-7,423,923 Capacitor supported precharging of memory digit lines
Circuits and methods are provided for precharging pairs of many digit lines. The final precharge voltage of the digit lines is different from the average of the...
US-7,423,922 Defective block handling in a flash memory device
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines...
US-7,423,919 Method and system for improved efficiency of synchronous mirror delays and delay locked loops
A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and...
US-7,423,918 Memory device having data paths with multiple speeds
A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of...
US-7,423,676 Asymmetric comparator for use in pixel oversaturation detection
An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are...
US-7,423,476 Current mirror circuit having drain-source voltage clamp
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output...
US-7,423,465 Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction...
A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal....
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