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Patent # Description
US-7,408,140 Pixel with spatially varying metal route positions
A method for configuring an image sensor including an array of pixels having an optical center, each pixel of the array including a metal segment disposed in a...
US-7,407,892 Deposition methods
The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is...
US-7,407,885 Methods of forming electrically conductive plugs
A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An...
US-7,407,830 CMOS image sensor and method of fabrication
A CMOS imaging device including a two pixel detection system for red, green, and blue light. One pixel detects red and blue light and another pixel detects green...
US-7,407,337 Cam-locking positioning mechanism
A locking positioning mechanism includes a first element and a second element, the first element and second element rotatable relative to one another about a...
US-7,406,608 Fast and compact circuit for bus inversion
A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog...
US-7,406,216 Method and apparatus for distributed analyses of images
A method and apparatus for intelligent distributed analyses of images including capturing the images and analyzing the captured images, where feature information...
US-7,405,966 Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
US-7,405,552 Semiconductor temperature sensor with high sensitivity
An temperature sensor circuit is disclosed. In one embodiment, the temperature sensor comprises an input circuit with a current mirror for forcing a current down...
US-7,405,487 Method and apparatus for removing encapsulating material from a packaged microelectronic device
A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at...
US-7,405,463 Gate dielectric antifuse circuit to protect a high-voltage transistor
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse...
US-7,405,455 Semiconductor constructions and transistor gates
One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer....
US-7,405,454 Electronic apparatus with deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
US-7,405,447 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
US-7,405,444 Micro-mechanically strained semiconductor film
A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process...
US-7,405,438 Capacitor constructions and semiconductor structures
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second...
US-7,405,414 Method and apparatus for patterning a workpiece
The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto...
US-7,405,385 Micro-lens configuration for small lens focusing in digital imaging devices
An improved image sensor wherein a first micro-lens array comprised of one or more micro-lenses is positioned over a cavity such that incoming light is focused...
US-7,405,110 Methods of forming implant regions relative to transistor gates
The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed,...
US-7,405,101 CMOS imager with selectively silicided gate
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the...
US-7,405,007 Semiconductor having a substantially uniform layer of electroplated metal
A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of...
US-7,404,719 Contact block and electrical connecting apparatus
A contact block includes a contact having a pair of contact pieces spaced apart, and an electrically insulating combining block for combining the contact pieces....
US-7,404,683 Printer
In a printer, when a cover is closed, a paper issuing path, and a paper setting path are formed downstream from a cutter mechanism in a paper transport path. The...
US-7,404,162 Buffering technique using structured delay skewing
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to...
US-7,404,124 On-chip sampling circuit and method
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers....
US-7,404,071 Memory modules having accurate operating current values stored thereon and methods for fabricating and...
Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance....
US-7,404,066 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,404,033 Method for reading while writing to a single partition flash memory
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient...
US-7,403,631 Electro-acoustic transducer
The two coil spring terminals have the structure of double coil spring terminal including a small diameter coil spring terminal and a large diameter coil spring...
US-7,403,444 Selectable memory word line deactivation
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to...
US-7,403,425 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,403,423 Sensing scheme for low-voltage flash memory
Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their...
US-7,403,419 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,416 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,060 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
US-7,403,044 Method of producing balanced data output
Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that...
US-7,403,033 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,402,908 Intermediate semiconductor device structures
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive,...
US-7,402,902 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,402,879 Layered magnetic structures having improved surface planarity for bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
US-7,402,876 Zr-- Sn--Ti--O films
A dielectric film containing Zr--Sn--Ti--O formed by atomic layer deposition using a TiI.sub.4 precursor and a method of fabricating such a dielectric film...
US-7,402,861 Memory cells and select gates of NAND memory arrays
A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric...
US-7,402,850 Back-side trapped non-volatile memory device
Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with...
US-7,402,833 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication
A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD...
US-7,402,789 Methods for pixel binning in an image sensor
Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned...
US-7,402,533 Masking without photolithography during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions,...
US-7,402,526 Plasma processing, deposition, and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...
US-7,402,518 Atomic layer deposition methods
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in...
US-7,402,516 Method for making integrated circuits
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,402,512 High aspect ratio contact structure with reduced silicon consumption
A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is...
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