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Patent # Description
US-7,479,413 Method for fabricating semiconductor package with circuit side polymer layer
A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a...
US-7,479,206 Apparatus for in-situ optical endpointing on web-format planarizing machines in mechanical or...
Polishing pads, planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies. The...
US-RE40,623 Method and apparatus for identifying integrated circuits
An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic...
US-7,478,032 Method and system for selecting compatible processors to add to a multiprocessor computer
A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program...
US-7,477,570 Sequential access memory with system and method
A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality...
US-7,477,557 256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array...
US-7,477,556 256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array...
US-7,477,554 Data retention kill function
A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and...
US-7,477,542 Split gate flash memory cell with ballistic injection
A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of...
US-7,477,306 Method and apparatus for improving pixel output swing in imager sensors
A bias readout circuit is disclosed for use in reading out a pixel of an imager system. The bias readout circuit includes a circuit portion which mirrors an...
US-7,477,304 Two narrow band and one wide band color filter for increasing color image sensor sensitivity
A color filter to increase the low light sensitivity of an image sensor. The color filter has two narrow band color filters and one wide band filter. Also...
US-7,477,298 Anti-eclipsing circuit for image sensors
An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection...
US-7,476,955 Die package having an adhesive flow restriction area
A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element....
US-7,476,933 Vertical gated access transistor
According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow...
US-7,476,927 Scalable multi-functional and multi-level nano-crystal non-volatile memory device
A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two...
US-7,476,925 Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,476,861 Passenger detection apparatus
A passenger detection device that determines whether a passenger sits in a passenger seat or backseat, and if YES, determines whether the passenger is an adult...
US-7,476,836 Multi-point correlated sampling for image sensors
An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating...
US-7,476,588 Methods of forming NAND cell units with string gates of various widths
Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string...
US-7,476,586 NOR flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor...
US-7,476,556 Systems and methods for plasma processing of microfeature workpieces
Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber...
US-7,476,305 Recovery system for platinum plating bath
A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation...
US-7,476,277 Apparatus for improving stencil/screen print quality
A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a...
US-7,475,137 Methods of operating portable computerized device with network security
A multi-level network security system is disclosed for a computer host device coupled to at least one computer network. The system including a secure network...
US-7,474,846 Method and apparatus of determining the best focus position of a lens
A method and apparatus for accurately auto focusing a lens of an imaging device. An imaged scene is split into an array of zones. The minimum and maximum...
US-7,474,560 Non-volatile memory with both single and multiple level cells
Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed...
US-7,474,111 Electrical probe assembly with guard members for the probes
The probe assembly has a plurality of probes, a probe base provided with the probes, and a plurality of guard members provided on the probe base. Each probe has...
US-7,473,956 Atomic layer deposition of metal oxide and/or low assymmetrical tunnel barrier interpoly insulators
Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The...
US-7,473,662 Metal-doped alumina and layers thereof
A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate...
US-7,473,645 Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate
The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and...
US-7,473,644 Method for forming controlled geometry hardmasks including subresolution elements
Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of...
US-7,473,637 ALD formed titanium nitride films
The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices....
US-7,473,615 Semiconductor processing methods
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can...
US-7,473,613 Terraced film stack
A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses...
US-7,473,596 Methods of forming memory cells
An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor...
US-7,473,582 Method for fabricating semiconductor component with thinned substrate having pin contacts
A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor...
US-7,472,392 Method for load balancing an n-dimensional array of parallel processing elements
One aspect of the present invention relates to a method for balancing the load of an n-dimensional array of processing elements (PEs), wherein each dimension of...
US-7,472,248 Techniques for generating serial presence detect contents
Techniques are presented for automatically generating Serial Presence Detect (SPD) contents. Standards for specific values associated with SPD contents are...
US-7,471,565 Reducing effects of program disturb in a memory device
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on...
US-7,471,538 Memory module, system and method of making same
A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices...
US-7,471,535 Programable identification circuitry
An integrated circuit has been described that includes a user programmable identification code register. The register can be programmed by the user to emulate...
US-7,471,228 Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,471,227 Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter
In accordance with one embodiment, there is provided a pipelined analog-to-digital converter (ADC) device. The pipelined ADC includes a first stage and a second...
US-7,471,130 Graduated delay line for increased clock skew correction circuit operating range
Clock synchronization and skew adjustment circuits are described that utilize varying unit delay elements in their delay lines in either a graduated or a stepped...
US-7,471,095 Electrical connecting apparatus and method for use thereof
An electrical connecting apparatus is used for electrical inspection of a device under test having electrodes each of which a recess is formed on a flat upside....
US-7,470,882 Reduction in size of column sample and hold circuitry in a CMOS imager
Improved column sample-and-hold (CSH) circuitry particularly useful in a CMOS imager is disclosed. In the improved circuitry layout, the overall column height of...
US-7,470,638 Systems and methods for manipulating liquid films on semiconductor substrates
A semiconductor substrate undergoing processing to fabricate integrated circuit devices thereon is spun about a rotational axis while introducing liquid onto a...
US-7,470,635 Method of depositing a silicon dioxide-comprising layer in the fabrication of integrated circuitry, methods of...
This invention includes methods of depositing silicon dioxide comprising layers in the fabrication of integrated circuitry, methods of forming trench isolation,...
US-7,470,632 Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
A substrate is positioned within a deposition chamber. At least two gaseous precursors are fed to the chamber which collectively comprise silicon, an oxidizer...
US-7,470,631 Methods for fabricating residue-free contact openings
A two-step via cleaning process that removes metal polymer and oxide polymer residues from a via with substantially no damage to the via or underlying structures...
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