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Programmable multiple texture combine circuit for a graphics processing
system and method for use thereof
The present invention is directed toward a texture combine circuit for generating fragment graphics data for a pixel in a graphics processing system. The texture...
Memory system having multiple address allocation formats and method for
A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory...
Interposers with flexible solder pad elements
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
Method and apparatus providing CMOS imager device pixel with transistor
having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
Microelectronic imagers with curved image sensors and methods for
manufacturing microelectronic imagers
Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes...
Method and apparatus for adjusting feature size and position
Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and...
Electronic apparatus, silicon-on-insulator integrated circuits, and
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate....
Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched...
High coupling memory cell
A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric...
Module assembly and method for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array...
Method of forming non-volatile resistance variable devices and method of
forming a programmable memory cell of...
A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises...
Plasma enhanced chemical vapor deposition method of forming titanium
silicide comprising layers
Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl.sub.4 and at least one silane are first fed to...
Through-hole conductors for semiconductor substrates and system for making
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
Split embedded DRAM processor
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural...
Method and system for aggregating and combining manufacturing data for
A method and system for aggregating and combining manufacturing data for analysis for the purposes of increasing manufacturing efficiency and reducing...
Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
Multiple select gate architecture
Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing...
Compliant contact pin assembly and card system
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
Integrated circuit and seed layers
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit...
Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another...
Strained Si/SiGe structures by ion implantation
One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium...
Image sensor having pinned floating diffusion diode
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
Composite dielectric forming methods and composite dielectrics
A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide...
Protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
Methods and apparatus for forming rhodium-containing layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L.sub.yRhY.sub.z is provided. Also...
Methods of forming metal-containing structures
The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The...
Backside method for fabricating semiconductor components with conductive
A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a...
Method for forming a storage cell capacitor compatible with high
dielectric constant materials
Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the...
Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
Methods of forming pluralities of capacitors
The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on...
Atomic layer deposition of Zr.sub.x Hf.sub.y Sn.sub.1-x-y O.sub.2 films as
high k gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) and tin oxide (SnO.sub.2)...
Plasma enhanced chemical vapor deposition method of forming titanium
silicide comprising layers
Chemical vapor deposition methods of forming titanium suicide including layers on substrates are disclosed. TiCl.sub.4 and at least one silane are first fed to...
Deposition methods for improved delivery of metastable species
A method of providing material into a deposition chamber is provided. A reservoir is in fluid communication with the deposition chamber. A metastable specie is...
In a force cutting type paper cutter, a movable blade includes a pair of right and left edges having a V shape. These right and left edges are intersected and...
Methods and apparatus for a flexible circuit interposer
Methods and apparatus for testing a semiconductor device are disclosed. A flexible circuit interposer includes a flexible circuit substrate which allows in-situ...
Program failure recovery
A method of operating a memory device when a program failure occurs is provided. The method includes preserving first data within the memory device and...
System and method for transmitting data packets in a computer system
having a memory hub architecture
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled...
Multi-function floating point arithmetic pipeline
A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product...
Correlation-based color mosaic interpolation adjustment using luminance
Processing a digitized image signal includes selectively adjusting interpolated color values on the basis of correlations between pre-identified reference...
DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as...
Memory block erasing in a flash memory device
The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory...
Low voltage sense amplifier for operation under a reduced bit line bias
A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (V.sub.cc), generates a regulated...
Semiconductor memory device with high permeability composite films to
reduce noise in high speed interconnects
A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
Camera module with dust trap
A camera module for capturing an image. The camera module including an image sensor including a die mounted on a substrate, a housing coupled with the substrate...
Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
Method for fabricating semiconductor components with conductive spring
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
Programmable array logic or memory with p-channel devices and asymmetrical
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
Semiconductor structures and memory device constructions
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
Imager floating diffusion region and process for forming same
The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a...