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Patent # Description
US-7,391,008 Method and system for wavelength-dependent imaging and detection using a hybrid filter
Apparatus and methods for wavelength-dependent detection are provided. A detector includes a hybrid filter having unpatterned and patterned filter layers and at...
US-7,390,756 Atomic layer deposited zirconium silicon oxide films
A dielectric layer containing an atomic layer deposited zirconium silicon oxide film disposed in an integrated circuit and a method of fabricating such a...
US-7,390,746 Multiple deposition for integration of spacers in pitch multiplication process
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the...
US-7,390,740 Sloped vias in a substrate, spring-like contacts, and methods of making
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed...
US-7,390,738 Fabrication of semiconductor devices using anti-reflective coatings
Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface...
US-7,390,712 Methods of enhancing capacitors in integrated circuits
Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The...
US-7,390,710 Protection of tunnel dielectric using epitaxial silicon
Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the...
US-7,390,690 Imager light shield
An improved imager pixel arrangement having a light shield over the pixel circuitry, but below the conductive interconnect layers of the pixel. The light shield...
US-7,390,687 Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
Microelectronic imagers with shaped image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device...
US-7,390,685 Ultra-shallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,389,581 Method of forming compliant contact structures
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a...
US-D571,684 Storage device bracelet
US-7,389,465 Error detection and correction scheme for a memory device
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are...
US-7,389,451 Memory redundancy with programmable control
A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is...
US-7,389,369 Active termination control
A method and apparatus are provided for active termination control in a memory. In an embodiment, the memory turns on active termination based on information...
US-7,389,364 Apparatus and method for direct memory access in a hub-based memory system
A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving...
US-7,388,801 Reduction of fusible links and associated circuitry on memory dies
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among...
US-7,388,794 Individual I/O modulation in memory devices
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are...
US-7,388,789 NAND memory device and programming methods
A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled...
US-7,388,779 Multiple level programming in a non-volatile device
The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the...
US-7,388,608 Sample and hold circuit and active pixel sensor array sampling system utilizing same
An active pixel sensor array sampling system includes a plurality of video circuits and reset circuits. A video circuit generates a video voltage from each one...
US-7,388,462 Integrated circuit inductors
The invention relates to an inductor comprising a plurality of interconnected conductive segments interwoven with a substrate. The inductance of the inductor is...
US-7,388,391 Method for evaluating at least one electrical conducting structure of an electronic component
An apparatus and method for evaluating the integrity of each contact pin of an electronic component having multiple contact pins. In one embodiment, the...
US-7,388,294 Semiconductor components having stacked dice
A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for...
US-7,388,290 Spacer patterned, high dielectric constant capacitor and methods for fabricating the same
A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area...
US-7,388,289 Local multilayered metallization
An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth,...
US-7,388,251 Non-planar flash memory array with shielded floating gates on silicon mesas
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of...
US-7,388,248 Dielectric relaxation memory
A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site...
US-7,388,246 Lanthanide doped TiO.sub.x dielectric films
A dielectric film containing lanthanide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable dielectric layer having an...
US-7,388,241 Pinned photodiode structure and method of formation
An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface...
US-7,388,239 Frame shutter pixel with an isolated storage node
A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent...
US-7,388,183 Low dark current pixel with a guard drive active photodiode
A method and apparatus for reducing thermally generated dark current in a CMOS imaging device is disclosed. A photodiode within the imaging device is kept...
US-7,387,959 Method of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed...
US-7,387,940 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,387,939 Methods of forming semiconductor structures and capacitor devices
The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the...
US-7,387,912 Packaging of electronic chips with air-bridge structures
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly...
US-7,387,909 Methods of forming assemblies displaying differential negative resistance
The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at...
US-7,387,908 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region...
US-7,387,902 Methods for packaging image sensitive electronic devices
The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS...
US-7,387,866 Photolithography process using multiple anti-reflective coatings
A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers...
US-7,387,853 Use of a planarizing layer to improve multilayer performance in ultraviolet masks
The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet ("EUV") photolithographic process. The EUV reticle comprises a...
US-7,387,685 Apparatus and method for depositing materials onto microelectronic workpieces
Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto...
US-7,387,119 Dicing saw with variable indexing capability
A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be...
US-7,386,689 Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be...
US-7,386,660 CAM with automatic writing to the next free address
A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid...
US-7,386,657 Random access interface in a serial memory device
A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address...
US-7,386,649 Multiple processor system and method including multiple memory hub modules
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly...
US-7,386,186 Apparatus and method for processing images
A method and apparatus for processing an image. Specifically, one exemplary embodiment of the method comprises inputting an image into a pixel array producing...
US-7,385,871 Apparatus for memory device wordline
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a...
US-7,385,868 Method of refreshing a PCRAM memory device
A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require...
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