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Patent # Description
US-7,399,657 Ball grid array packages with thermally conductive containers
Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die...
US-7,399,499 Methods of gas delivery for deposition processes and methods of depositing material on a substrate
Methods for depositing material onto workpieces, methods of controlling the delivery of gases in deposition processes, and apparatus for depositing materials...
US-7,399,424 Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-7,398,595 Method for forming a storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed...
US-7,398,412 Measure controlled delay with duty cycle control
The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to...
US-7,398,358 Method and apparatus for high performance branching in pipelined microsystems
A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates...
US-7,398,342 Active termination control
A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory....
US-7,397,712 Pre-emphasis for strobe signals in memory device
Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for...
US-7,397,711 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required...
US-7,397,689 Resistive memory device
A system having a memory cell. In certain embodiments, the memory cell includes a resistive memory element, an access transistor having a gate, a first terminal,...
US-7,397,509 High dynamic range imager with a rolling shutter
A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the imager...
US-7,397,503 Systems and methods for reducing artifacts caused by illuminant flicker
Methods for reducing artifacts caused by illuminant flicker are provided. One such method comprises: providing pixel circuits; and operating the pixel circuits...
US-7,397,479 Programmable multiple texture combine circuit for a graphics processing system and method for use thereof
The present invention is directed toward a texture combine circuit for generating fragment graphics data for a pixel in a graphics processing system. The texture...
US-7,397,477 Memory system having multiple address allocation formats and method for use thereof
A system and method for decoding memory addresses for accessing a memory system having a plurality of blocks of memory for storing data at addressable memory...
US-7,397,129 Interposers with flexible solder pad elements
Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes...
US-7,397,075 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
US-7,397,066 Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes...
US-7,396,781 Method and apparatus for adjusting feature size and position
Variations in the pitch of features formed using pitch multiplication are minimized by separately forming at least two sets of spacers. Mandrels are formed and...
US-7,396,779 Electronic apparatus, silicon-on-insulator integrated circuits, and fabrication methods
An electronic apparatus includes an insulative substrate containing an aluminum-based glass and a layer containing a semiconductive material over the substrate....
US-7,396,774 Methods for forming an enriched metal oxide surface
Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state are provided. A metal oxide surface that is enriched...
US-7,396,720 High coupling memory cell
A first dielectric layer is formed over a substrate. A single layer first conductive layer that acts as a floating gate is formed over the first dielectric...
US-7,396,702 Module assembly and method for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array...
US-7,396,699 Method of forming non-volatile resistance variable devices and method of forming a programmable memory cell of...
A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises...
US-7,396,570 Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers
Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl.sub.4 and at least one silane are first fed to...
US-7,396,447 Through-hole conductors for semiconductor substrates and system for making same
A method, structure and system for forming a through-hole conductor in a semiconductor substrate includes forming a hole having an inner surface from a first...
US-7,395,409 Split embedded DRAM processor
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural...
US-7,395,130 Method and system for aggregating and combining manufacturing data for analysis
A method and system for aggregating and combining manufacturing data for analysis for the purposes of increasing manufacturing efficiency and reducing...
US-7,394,699 Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
US-7,394,693 Multiple select gate architecture
Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing...
US-7,394,267 Compliant contact pin assembly and card system
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
US-7,394,157 Integrated circuit and seed layers
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit...
US-7,394,142 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another...
US-7,394,111 Strained Si/SiGe structures by ion implantation
One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium...
US-7,394,056 Image sensor having pinned floating diffusion diode
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,393,798 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,393,796 Composite dielectric forming methods and composite dielectrics
A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide...
US-7,393,789 Protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
US-7,393,785 Methods and apparatus for forming rhodium-containing layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L.sub.yRhY.sub.z is provided. Also...
US-7,393,783 Methods of forming metal-containing structures
The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The...
US-7,393,770 Backside method for fabricating semiconductor components with conductive interconnects
A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a...
US-7,393,753 Method for forming a storage cell capacitor compatible with high dielectric constant materials
Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the...
US-7,393,743 Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
US-7,393,741 Methods of forming pluralities of capacitors
The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on...
US-7,393,736 Atomic layer deposition of Zr.sub.x Hf.sub.y Sn.sub.1-x-y O.sub.2 films as high k gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) and tin oxide (SnO.sub.2)...
US-7,393,563 Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers
Chemical vapor deposition methods of forming titanium suicide including layers on substrates are disclosed. TiCl.sub.4 and at least one silane are first fed to...
US-7,393,562 Deposition methods for improved delivery of metastable species
A method of providing material into a deposition chamber is provided. A reservoir is in fluid communication with the deposition chamber. A metastable specie is...
US-7,392,731 Paper cutter
In a force cutting type paper cutter, a movable blade includes a pair of right and left edges having a V shape. These right and left edges are intersected and...
US-7,392,584 Methods and apparatus for a flexible circuit interposer
Methods and apparatus for testing a semiconductor device are disclosed. A flexible circuit interposer includes a flexible circuit substrate which allows in-situ...
US-7,392,436 Program failure recovery
A method of operating a memory device when a program failure occurs is provided. The method includes preserving first data within the memory device and...
US-7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled...
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