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Patent # Description
US-7,433,250 Sense amplifier circuit
An equalization circuit may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An...
US-7,433,249 Apparatus with equalizing voltage generation circuit and methods of use
A memory device includes an equalization voltage generator. The equalization voltage generator includes an oscillator and a charge pump to produce a first...
US-7,433,248 System and method for enhanced mode register definitions
Apparatus and methods for increasing a number of selectable options for an operating mode. A number of selectable options for an operating mode is increased by...
US-7,433,237 Memory utilizing oxide nanolaminates
One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the...
US-7,433,231 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,433,227 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of...
US-7,432,968 CMOS image sensor with reduced 1/f noise
A CMOS image sensor includes a plurality of pixel circuits. Each pixel circuit includes a plurality of transistors. The image sensor includes a controller for...
US-7,432,774 Microstrip line dielectric overlay
A printed circuit board has a dielectric constant different from the dielectric constant of free space, with at least two microstrip lines routed adjacent to one...
US-7,432,604 Semiconductor component and system having thinned, encapsulated dice
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,432,600 System having semiconductor component with multiple stacked dice
A system includes a semiconductor component having a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking...
US-7,432,593 Semiconductor package assembly and method for electrically isolating modules
A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package...
US-7,432,562 SRAM devices, and electronic systems comprising SRAM devices
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
US-7,432,548 Silicon lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of...
US-7,432,546 Apparatus having a memory device with floating gate layer grain boundaries with oxidized portions
The present invention provides a flash memory integrated circuit and a method for fabricating the same. The method includes etching a gate stack that includes an...
US-7,432,540 Dual conversion gain gate and capacitor combination
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective...
US-7,432,491 Pixel with spatially varying sensor positions
An image sensor including a substrate, at least one metal layer, and a plurality of pixels arranged in array. Each pixel includes a sense element disposed in the...
US-7,432,214 Compositions for dissolution of low-k dielectric film, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
US-7,432,212 Methods of processing a semiconductor substrate
The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface....
US-7,432,197 Methods of patterning photoresist, and methods of forming semiconductor constructions
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between...
US-7,432,166 Methods of forming a nitrogen enriched region
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
US-7,432,152 Methods of forming HSG layers and devices
A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas...
US-7,432,148 Shallow trench isolation by atomic-level silicon reconstruction
Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to...
US-7,432,121 Isolation process and structure for CMOS imagers
A barrier implanted region of a first conductivity type formed in lieu of an isolation region of a pixel sensor cell that provides physical and electrical...
US-7,432,025 Methods of forming reticles
The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes...
US-7,431,966 Atomic layer deposition method of depositing an oxide on a substrate
The invention includes atomic layer deposition methods of depositing an oxide on a substrate. In one implementation, a substrate is positioned within a...
US-7,431,773 Atomic layer deposition apparatus and method
An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first deposition precursor is fed...
US-7,431,225 Methods of operating a liquid vaporizer
The present invention is generally directed to a vaporizer with positive liquid shut-off. In one illustrative embodiment, the vaporizer is comprised of a body, a...
US-D578,062 Electroacoustic transducer
US-7,430,742 Method for load balancing a line of parallel processing elements
A method for balancing the load of a parallel processing system having parallel processing elements (PEs) linked serially in a line with first and second ends,...
US-7,430,002 Digital imaging system and method for adjusting image-capturing parameters using image comparisons
A digital imaging system and method for manually adjusting the image-capturing parameters of a digital imaging device of the system utilizes a comparative image...
US-7,429,767 High performance multi-level non-volatile memory device
Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping...
US-7,429,763 Memory with strained semiconductor by wafer bonding with misorientation
One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding...
US-7,429,541 Method of forming trench isolation in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,429,536 Methods for forming arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-7,429,535 Use of a plasma source to form a layer during the formation of a semiconductor device
A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer...
US-7,429,515 Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO.sub.2 gate oxides...
US-7,429,514 Use of selective oxidation to form asymmetrical oxide features during the manufacture of a semiconductor device
A sidewall oxidation process for use during the formation of a transistor such as a flash memory cell allows for improved control of a gate oxide profile. The...
US-7,429,494 Microelectronic imagers with optical devices having integral reference features and methods for manufacturing...
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed...
US-7,428,714 Line width error check
A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum...
US-7,428,687 Memory controller method and system compensating for memory cell data losses
A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing...
US-7,428,672 Apparatus and methods for testing memory devices
Each match line of a memory device such as a content addressable memory (CAM) device and a related part of a priority encoder can be separately tested. In test...
US-7,428,644 System and method for selective memory module power management
A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the...
US-7,428,373 Delivery of solid chemical precursors
Systems and methods are provided for delivering solid precursors. In certain embodiments of the present application, a flow monitor, pressure sensor, or...
US-7,428,284 Phase detector and method providing rapid locking of delay-lock loops
A delay-lock loop includes a dual mode phase detector. The dual mode phase detector includes a single edge phase detector that generates output signals...
US-7,428,181 Semiconductor device with self refresh test mode
A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or...
US-7,428,173 Low power NROM memory devices
A buried bipolar junction is provided in a charge trapping transistor memory device. During a write operation electrons are injected into a surface depletion...
US-7,428,103 Gapless microlens array and method of fabrication
A microlens array with reduced or no empty space between individual microlenses and a method for forming the same. The microlens array is formed by patterning a...
US-7,427,869 Resilient contact probe apparatus
Carriers comprising a carrier body having a plurality of openings holding a plurality of resilient contact probes are disclosed. A number of different...
US-7,427,837 Rear plate for plasma display panel with barrier ribs having specific width characteristics
Disclosed is a rear plate of a plasma display panel. In the rear plate, barrier ribs are formed by etching a baked barrier rib layer, so that the completed...
US-7,427,811 Semiconductor substrate
A semiconductor wafer having a high degree of thinness and exhibiting an enhanced strength state. A layer of tenacious reinforcement material is disposed over a...
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