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Patent # Description
US-7,411,297 Microfeature devices and methods for manufacturing microfeature devices
Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The...
US-7,411,286 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,411,262 Self-aligned, low-resistance, efficient memory array
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed...
US-7,411,255 Dopant barrier for doped glass in memory devices
A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes...
US-7,411,254 Semiconductor substrate
The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a...
US-7,411,237 Lanthanum hafnium oxide dielectrics
Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers,...
US-7,410,918 Systems and methods for forming metal oxides using alcohols
A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,410,917 Atomic layer deposited Zr-Sn-Ti-O films using TiI.sub.4
Various structures having a dielectric film containing Zr--Sn--Ti--O formed by atomic layer deposition using a TiI.sub.4 precursor and a method of fabricating...
US-7,410,911 Method for stabilizing high pressure oxidation of a semiconductor device
A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are...
US-7,410,910 Lanthanum aluminum oxynitride dielectric films
Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of...
US-7,410,903 Methods of patterning substrates
The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent...
US-7,410,898 Methods of fabricating interconnects for semiconductor components
In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an...
US-7,410,867 Vertical transistor with horizontal gate layers
Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable...
US-7,410,863 Methods of forming and using memory cell structures
A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator...
US-7,410,856 Methods of forming vertical transistors
A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess...
US-7,410,748 Method of etching materials patterned with a single layer 193nm resist
A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom...
US-7,410,668 Methods, systems, and apparatus for uniform chemical-vapor depositions
Integrated circuits, the key components in thousands of electronic and computer products, are generally built layer by layer on a silicon substrate. One common...
US-7,409,762 Method for fabricating an interconnect for semiconductor components
A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on...
US-7,409,529 Method and apparatus for a shift register based interconnection for a massively parallel processor array
A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the...
US-7,409,493 Top/bottom symmetrical protection scheme for flash
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The...
US-7,408,828 System and method for reducing power consumption during extended refresh periods of dynamic random access...
A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate...
US-7,408,825 Apparatus and method for repairing a semiconductor memory
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit...
US-7,408,822 Alignment of memory read data and clocking
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To...
US-7,408,814 Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
US-7,408,813 Block erase for volatile memory
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a...
US-7,408,810 Minimizing effects of program disturb in a memory device
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the...
US-7,408,808 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,408,807 NAND string wordline delay reduction
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line...
US-7,408,805 Reducing delays in word line selection
Delays in selecting word lines of a NAND memory device are reduced by respectively connecting conductive straps to word lines of a subset of the word lines of...
US-7,408,577 Biasing scheme for large format CMOS active pixel sensors
An image sensor includes circuitry compensating for voltage drops in a V.sub.SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel...
US-7,408,496 Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,408,394 Measure control delay and method having latching circuit integral with delay circuit
A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A...
US-7,408,265 Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor...
An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is...
US-7,408,255 Assembly for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array...
US-7,408,237 Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
US-7,408,216 Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces
Some embodiments of the invention include a memory cell having a vertical transistor and a trench capacitor. The trench capacitor includes a capacitor plate with...
US-7,408,140 Pixel with spatially varying metal route positions
A method for configuring an image sensor including an array of pixels having an optical center, each pixel of the array including a metal segment disposed in a...
US-7,407,892 Deposition methods
The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is...
US-7,407,885 Methods of forming electrically conductive plugs
A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An...
US-7,407,830 CMOS image sensor and method of fabrication
A CMOS imaging device including a two pixel detection system for red, green, and blue light. One pixel detects red and blue light and another pixel detects green...
US-7,407,337 Cam-locking positioning mechanism
A locking positioning mechanism includes a first element and a second element, the first element and second element rotatable relative to one another about a...
US-7,406,608 Fast and compact circuit for bus inversion
A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog...
US-7,406,216 Method and apparatus for distributed analyses of images
A method and apparatus for intelligent distributed analyses of images including capturing the images and analyzing the captured images, where feature information...
US-7,405,966 Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
US-7,405,552 Semiconductor temperature sensor with high sensitivity
An temperature sensor circuit is disclosed. In one embodiment, the temperature sensor comprises an input circuit with a current mirror for forcing a current down...
US-7,405,487 Method and apparatus for removing encapsulating material from a packaged microelectronic device
A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at...
US-7,405,463 Gate dielectric antifuse circuit to protect a high-voltage transistor
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse...
US-7,405,455 Semiconductor constructions and transistor gates
One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer....
US-7,405,454 Electronic apparatus with deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
US-7,405,447 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
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