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Patent # Description
US-7,395,130 Method and system for aggregating and combining manufacturing data for analysis
A method and system for aggregating and combining manufacturing data for analysis for the purposes of increasing manufacturing efficiency and reducing...
US-7,394,699 Sense amplifier for a non-volatile memory device
The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the...
US-7,394,693 Multiple select gate architecture
Non-volatile memory devices including multiple series-coupled select gates on the drain and/or source ends of strings of non-volatile memory cells. By utilizing...
US-7,394,267 Compliant contact pin assembly and card system
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
US-7,394,157 Integrated circuit and seed layers
Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit...
US-7,394,142 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another...
US-7,394,111 Strained Si/SiGe structures by ion implantation
One aspect of this disclosure relates to a method for forming a strained silicon over silicon germanium (Si/SiGe) structure. In various embodiments, germanium...
US-7,394,056 Image sensor having pinned floating diffusion diode
The present invention provides an image sensor having a pinned floating diffusion region in addition to a pinned photodiode. The pinned floating diffusion region...
US-7,393,798 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,393,796 Composite dielectric forming methods and composite dielectrics
A composite dielectric forming method includes atomic layer depositing alternate layers of hafnium oxide and lanthanum oxide over a substrate. The hafnium oxide...
US-7,393,789 Protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction...
US-7,393,785 Methods and apparatus for forming rhodium-containing layers
A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula L.sub.yRhY.sub.z is provided. Also...
US-7,393,783 Methods of forming metal-containing structures
The invention includes methods of forming metal-containing layers. The layers can, in particular aspects, consist essentially of metal, or consist of metal. The...
US-7,393,770 Backside method for fabricating semiconductor components with conductive interconnects
A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a...
US-7,393,753 Method for forming a storage cell capacitor compatible with high dielectric constant materials
Described are integrated circuit electrodes and method for fabricating an electrode, which include, in an embodiment forming a silicon, first portion of the...
US-7,393,743 Methods of forming a plurality of capacitors
The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a...
US-7,393,741 Methods of forming pluralities of capacitors
The invention comprises methods of forming pluralities of capacitors. In one implementation, metal is formed over individual capacitor storage node locations on...
US-7,393,736 Atomic layer deposition of Zr.sub.x Hf.sub.y Sn.sub.1-x-y O.sub.2 films as high k gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate dielectric of zirconium oxide (ZrO.sub.2), hafnium oxide (HfO.sub.2) and tin oxide (SnO.sub.2)...
US-7,393,563 Plasma enhanced chemical vapor deposition method of forming titanium silicide comprising layers
Chemical vapor deposition methods of forming titanium suicide including layers on substrates are disclosed. TiCl.sub.4 and at least one silane are first fed to...
US-7,393,562 Deposition methods for improved delivery of metastable species
A method of providing material into a deposition chamber is provided. A reservoir is in fluid communication with the deposition chamber. A metastable specie is...
US-7,392,731 Paper cutter
In a force cutting type paper cutter, a movable blade includes a pair of right and left edges having a V shape. These right and left edges are intersected and...
US-7,392,584 Methods and apparatus for a flexible circuit interposer
Methods and apparatus for testing a semiconductor device are disclosed. A flexible circuit interposer includes a flexible circuit substrate which allows in-situ...
US-7,392,436 Program failure recovery
A method of operating a memory device when a program failure occurs is provided. The method includes preserving first data within the memory device and...
US-7,392,331 System and method for transmitting data packets in a computer system having a memory hub architecture
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled...
US-7,392,274 Multi-function floating point arithmetic pipeline
A scalable engine having multiple datapaths, each of which is a unique multi-function floating point pipeline capable of performing a four component dot product...
US-7,391,904 Correlation-based color mosaic interpolation adjustment using luminance gradients
Processing a digitized image signal includes selectively adjusting interpolated color values on the basis of correlations between pre-identified reference...
US-7,391,666 DRAM power bus control
A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as...
US-7,391,654 Memory block erasing in a flash memory device
The erase and verify method performs an erase operation and an erase verify read operation. If the erase verify read operation fails because unerased memory...
US-7,391,648 Low voltage sense amplifier for operation under a reduced bit line bias voltage
A regulated charge pump, regulated by a plurality of capacitor boost stages and separate from the memory device supply voltage (V.sub.cc), generates a regulated...
US-7,391,637 Semiconductor memory device with high permeability composite films to reduce noise in high speed interconnects
A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
US-7,391,466 Camera module with dust trap
A camera module for capturing an image. The camera module including an image sensor including a die mounted on a substrate, a housing coupled with the substrate...
US-7,391,243 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,391,117 Method for fabricating semiconductor components with conductive spring contacts
An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage...
US-7,391,072 Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers
Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are...
US-7,391,070 Semiconductor structures and memory device constructions
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions...
US-7,391,066 Imager floating diffusion region and process for forming same
The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a...
US-7,391,008 Method and system for wavelength-dependent imaging and detection using a hybrid filter
Apparatus and methods for wavelength-dependent detection are provided. A detector includes a hybrid filter having unpatterned and patterned filter layers and at...
US-7,390,756 Atomic layer deposited zirconium silicon oxide films
A dielectric layer containing an atomic layer deposited zirconium silicon oxide film disposed in an integrated circuit and a method of fabricating such a...
US-7,390,746 Multiple deposition for integration of spacers in pitch multiplication process
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the...
US-7,390,740 Sloped vias in a substrate, spring-like contacts, and methods of making
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. The vias are formed...
US-7,390,738 Fabrication of semiconductor devices using anti-reflective coatings
Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface...
US-7,390,712 Methods of enhancing capacitors in integrated circuits
Systems, devices, structures, and methods are described that inhibit dielectric degradation at high temperatures. An enhanced capacitor is discussed. The...
US-7,390,710 Protection of tunnel dielectric using epitaxial silicon
Layers of epitaxial silicon are used to protect the tunnel dielectric layer of a floating-gate memory cell from excessive oxidation or removal during the...
US-7,390,690 Imager light shield
An improved imager pixel arrangement having a light shield over the pixel circuitry, but below the conductive interconnect layers of the pixel. The light shield...
US-7,390,687 Microelectronic imagers with shaped image sensors and methods for manufacturing microelectronic imagers
Microelectronic imagers with shaped image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device...
US-7,390,685 Ultra-shallow photodiode using indium
The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to...
US-7,389,581 Method of forming compliant contact structures
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a...
US-D571,684 Storage device bracelet
US-7,389,465 Error detection and correction scheme for a memory device
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are...
US-7,389,451 Memory redundancy with programmable control
A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is...
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