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Patent # Description
US-7,386,186 Apparatus and method for processing images
A method and apparatus for processing an image. Specifically, one exemplary embodiment of the method comprises inputting an image into a pixel array producing...
US-7,385,871 Apparatus for memory device wordline
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a...
US-7,385,868 Method of refreshing a PCRAM memory device
A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require...
US-7,385,846 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,385,842 Magnetic memory having synthetic antiferromagnetic pinned layer
A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel...
US-7,385,547 Minimized differential SAR-type column-wide ADC for CMOS image sensors
An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential...
US-7,385,412 Systems and methods for testing microfeature devices
Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a...
US-7,385,298 Reduced-dimension microelectronic component assemblies with wire bonds and methods of making same
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,385,290 Electrochemical reaction cell for a combined barrier layer and seed layer
Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit...
US-7,385,259 Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device
A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method...
US-7,385,245 Low power memory subsystem with progressive non-volatility
The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that...
US-7,385,240 Storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed...
US-7,385,238 Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors
A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or...
US-7,385,232 CMOS imager with enhanced transfer of charge and low voltage operation and method of formation
A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region...
US-7,385,222 Thin film transistors and semiconductor constructions
A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a...
US-7,385,167 CMOS front end process compatible low stress light shield
An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding...
US-7,385,166 In-pixel kTC noise suppression using circuit techniques
A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within...
US-7,384,849 Methods of forming recessed access devices associated with semiconductor constructions
The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the...
US-7,384,847 Methods of forming DRAM arrays
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,384,840 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another...
US-7,384,805 Transfer mold semiconductor packaging processes
In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and...
US-7,384,727 Semiconductor processing patterning methods
The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming...
US-7,383,376 Apparatus and methods for storing data in a magnetic random access memory (MRAM)
An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of...
US-7,383,182 Systems and methods for speech recognition and separate dialect identification
A speech-to-text conversion system. The two-way speech recognition and dialect system comprises a computer system, an attached microphone assembly, and...
US-7,383,147 Dynamically adaptable semiconductor parametric testing
An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time...
US-7,382,678 Delay stage-interweaved analog DLL/PLL
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the...
US-7,382,667 Active termination circuit and method for controlling the impedance of external integrated circuit terminals
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage...
US-7,382,646 Memory architecture containing a high density memory array of semi-volatile or non-volatile memory elements
An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,...
US-7,382,639 System and method for optically interconnecting memory devices
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled...
US-7,382,408 Varying capacitance that receives signals from sensing elements
Capacitance on a readout line is varied while receiving a signal, from a light sensing pixel or other sensing element through the line. Capacitance can be varied...
US-7,382,407 High intrascene dynamic range NTSC and PAL imager
The invention provides a new method and apparatus for NTSC and PAL image sensors which employs fusion of adjacent row pixel charge samples to generate image data...
US-7,382,227 Portable computer supporting paging instructions
A portable computer is described that contains a circuit for receiving pages and performing security functions based on the received page. Once a page has been...
US-7,382,177 Voltage charge pump and method of operating the same
A voltage pump comprising a charging transistor responsive to a first control signal, the charging transistor operable to connect a node to a first voltage, a...
US-7,382,060 Semiconductor component having thinned die, polymer layers, contacts on opposing sides, and conductive vias...
A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps...
US-7,381,647 Methods and systems for planarizing microelectronic devices with Ge-Se-Ag layers
Microelectronic devices including a layer of germanium and selenium, optionally including up to 10 atomic percent silver, show promise for select applications....
US-7,381,591 Flip-chip adaptor package for bare die
A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or...
US-7,381,573 Self-aligned, low-resistance, efficient memory array
The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed...
US-7,380,328 Method of forming an inductor
The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of...
US-7,379,382 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,379,377 Memory array decoder
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match...
US-7,379,365 Method and apparatus for charging large capacitances
A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator...
US-7,379,336 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,379,315 Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier...
US-7,379,068 Memory system and method for improved utilization of read and write bandwidth of a graphics processing system
A system and method for processing graphics data which improves utilization of read and write bandwidth of a graphics processing system. The graphics processing...
US-7,378,891 Measure-controlled circuit with frequency control
Some embodiments include a delay locked circuit having multiple paths. A first path measures a timing of a first clock signal during a measurement. A second path...
US-7,378,737 Structures and methods to enhance copper metallization
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a...
US-7,378,736 Ball grid array structures having tape-based circuitry
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using...
US-7,378,723 Method and apparatus for decoupling conductive portions of a microelectronic device package
A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic...
US-7,378,719 Low leakage MIM capacitor
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a...
US-7,378,707 Scalable high density non-volatile memory cells in a contactless memory array
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion...
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