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Patent # Description
US-7,378,635 Method and apparatus for dark current and hot pixel reduction in active pixel image sensors
A method of operating an imager pixel that includes the act of applying a relatively small voltage on the gate of a transfer transistor during a charge...
US-7,378,354 Atomic layer deposition methods
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a...
US-7,378,353 High selectivity BPSG to TEOS etchant
An organic acid/fluoride-containing solution etchant having high selectivity for BPSG to TEOS. In an exemplary situation, a TEOS layer may be used to prevent...
US-7,378,342 Methods for forming vias varying lateral dimensions
Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening, a...
US-7,378,316 Method for fabricating semiconductor vertical NROM memory cells
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,378,313 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules
Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG)...
US-7,378,311 Method of forming memory cells in an array
The invention includes a 6F.sup.2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a...
US-7,378,290 Isolation circuit
An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a...
US-7,378,199 Micro-lenses and method for increasing area coverage and controlling shape of micro lenses
Micro-lenses for use in imagers and their method of manufacture from intermediate lens structures are described. Lithographic masks are used to remove unwanted...
US-7,378,129 Atomic layer deposition methods of forming conductive metal nitride comprising layers
This invention includes atomic layer deposition methods of forming conductive metal nitride comprising layers. In one implementation, an atomic layer deposition...
US-7,378,127 Chemical vapor deposition methods
A chemical vapor deposition apparatus includes a deposition chamber defined at least in part by chamber walls, a substrate holder inside the chamber, and at...
US-7,377,788 Electrical connecting apparatus and contact
An electrical connecting apparatus comprises: a base plate provided with a first and a second mounting portion groups respectively having a plurality of first...
US-7,377,018 Method of replacing a subpad of a polishing apparatus
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad...
US-D569,852 Microphone
US-D569,851 Microphone
US-D569,850 Microphone
US-7,376,874 Method of controlling a test mode of a circuit
A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an...
US-7,376,857 Method of timing calibration using slower data rate pattern
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device...
US-7,376,669 System for automatically initiating a computer security and/or screen saver mode
A system for automatically switching a computer to a password protected screen saver mode when a computer user leaves the proximity of the computer. The system...
US-7,376,244 Imaging surveillance system and method for event detection in low illumination
A surveillance system and method is provided for detecting and event and then capturing an image of the event under low illumination conditions. A camera...
US-7,376,025 Method and apparatus for semiconductor device repair with reduced number of programmable elements
An apparatus and method using a reduced number of fuses for enabling redundant memory blocks in a semiconductor memory is disclosed. In one embodiment, a...
US-7,376,024 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,375,892 Ellipsoidal gapless microlens array and method of fabrication
Ellipse-shaped microlenses focus light onto unbalanced photosensitive areas, increase area coverage for a gapless layout of microlenses, and allow pair-wise or...
US-7,375,793 Apparatus for photolithographic processing
Photolithographic processing apparatus and methods are disclosed. In one embodiment, a method of photolithographically patterning a surface of a substrate...
US-7,375,748 Differential readout from pixels in CMOS sensor
The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by...
US-7,375,573 De-emphasis system and method for coupling digital signals through capacitively loaded lines
A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals...
US-7,375,560 Method and apparatus for timing domain crossing
A timing domain crossing apparatus and method of transferring signals between timing domains are disclosed. A receiver samples a data signal with a sample clock...
US-7,375,554 Voltage level translator circuitry
Circuitry and methods for implementing voltage level translators at relatively low source voltages are provided. The circuitry and methods utilize voltage...
US-7,375,419 Stacked mass storage flash memory package
A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields...
US-7,375,414 High permeability layered films to reduce noise in high speed interconnects
This invention provides a structure and method for improved transmission line operation on integrated circuits. One method of the invention includes forming...
US-7,375,388 Device having improved surface planarity prior to MRAM bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
US-7,375,036 Anisotropic etch method
A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate...
US-7,375,033 Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the via,...
US-7,375,026 Local multilayered metallization
An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth,...
US-7,375,014 Methods of electrochemically treating semiconductor substrates
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,375,009 Method of forming a conductive via through a wafer
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-7,375,004 Method of making an isolation trench and resulting isolation trench
A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the...
US-7,374,993 Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
US-7,374,990 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,374,964 Atomic layer deposition of CeO.sub.2/Al.sub.2O.sub.3 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a nanolaminate layered dielectric layer of cerium oxide and aluminum oxide acting as a single dielectric layer...
US-7,374,617 Atomic layer deposition methods and chemical vapor deposition methods
The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave...
US-7,374,476 Method and apparatus for forming a planarizing pad having a film and texture elements for planarization of...
A planarizing pad for planarizing a microelectronic substrate, and a method and apparatus for forming the planarizing pad. In one embodiment, planarizing pad...
US-7,374,174 Small electrode for resistance variable devices
A memory element comprising first and second electrodes is provided. The first electrode is tapered such that a first end of the first electrode is larger than a...
US-7,373,645 Method for using extrema to load balance a loop of parallel processing elements
A method for balancing the load of a parallel processing system having a plurality of parallel processing elements arranged in a loop, each processing element...
US-7,373,575 Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured....
US-7,373,005 Compression system for integrated sensor devices
An imaging system incorporating adaptive compression which includes determining linear predictive differential residuals from an imager array pixel row. The...
US-7,372,768 Memory with address management
The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on...
US-7,372,756 Non-skipping auto-refresh in a DRAM
In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This...
US-7,372,751 Using redundant memory for extra features
Apparatus and methods are provided. A memory device has a memory array comprising primary and redundant portions. A redundancy circuit is coupled to the memory...
US-7,372,746 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may...
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