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Patent # Description
US-7,408,825 Apparatus and method for repairing a semiconductor memory
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit...
US-7,408,822 Alignment of memory read data and clocking
Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To...
US-7,408,814 Method and apparatus for filtering output data
Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a...
US-7,408,813 Block erase for volatile memory
A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a...
US-7,408,810 Minimizing effects of program disturb in a memory device
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the...
US-7,408,808 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,408,807 NAND string wordline delay reduction
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line...
US-7,408,805 Reducing delays in word line selection
Delays in selecting word lines of a NAND memory device are reduced by respectively connecting conductive straps to word lines of a subset of the word lines of...
US-7,408,577 Biasing scheme for large format CMOS active pixel sensors
An image sensor includes circuitry compensating for voltage drops in a V.sub.SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel...
US-7,408,496 Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two...
A mechanism for discharging parasitic capacitance at an input of an operational amplifier, which is shared between two stages of a pipelined analog-to-digital...
US-7,408,394 Measure control delay and method having latching circuit integral with delay circuit
A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A...
US-7,408,265 Use of a dual-tone resist to form photomasks including alignment mark protection, intermediate semiconductor...
An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is...
US-7,408,255 Assembly for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array...
US-7,408,237 Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
US-7,408,216 Device, system, and method for a trench capacitor having micro-roughened semiconductor surfaces
Some embodiments of the invention include a memory cell having a vertical transistor and a trench capacitor. The trench capacitor includes a capacitor plate with...
US-7,408,140 Pixel with spatially varying metal route positions
A method for configuring an image sensor including an array of pixels having an optical center, each pixel of the array including a metal segment disposed in a...
US-7,407,892 Deposition methods
The invention includes deposition methods and apparatuses which can be utilized during atomic layer deposition or chemical vapor deposition. A heated surface is...
US-7,407,885 Methods of forming electrically conductive plugs
A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An...
US-7,407,830 CMOS image sensor and method of fabrication
A CMOS imaging device including a two pixel detection system for red, green, and blue light. One pixel detects red and blue light and another pixel detects green...
US-7,407,337 Cam-locking positioning mechanism
A locking positioning mechanism includes a first element and a second element, the first element and second element rotatable relative to one another about a...
US-7,406,608 Fast and compact circuit for bus inversion
A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog...
US-7,406,216 Method and apparatus for distributed analyses of images
A method and apparatus for intelligent distributed analyses of images including capturing the images and analyzing the captured images, where feature information...
US-7,405,966 Magnetic tunneling junction antifuse device
An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the...
US-7,405,552 Semiconductor temperature sensor with high sensitivity
An temperature sensor circuit is disclosed. In one embodiment, the temperature sensor comprises an input circuit with a current mirror for forcing a current down...
US-7,405,487 Method and apparatus for removing encapsulating material from a packaged microelectronic device
A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at...
US-7,405,463 Gate dielectric antifuse circuit to protect a high-voltage transistor
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse...
US-7,405,455 Semiconductor constructions and transistor gates
One aspect of the invention encompasses a method of forming a semiconductor structure. A patterned line is formed to comprise a first layer and a second layer....
US-7,405,454 Electronic apparatus with deposited dielectric layers
An atomic layer deposited dielectric layer and a method of fabricating such a dielectric layer produce a reliable dielectric layer having an equivalent oxide...
US-7,405,447 Silicon rich barrier layers for integrated circuit devices
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to...
US-7,405,444 Micro-mechanically strained semiconductor film
A semiconductor structure embodiment comprises a semiconductor membrane with local strained areas. The membrane with local strained areas is formed by a process...
US-7,405,438 Capacitor constructions and semiconductor structures
The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second...
US-7,405,414 Method and apparatus for patterning a workpiece
The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto...
US-7,405,385 Micro-lens configuration for small lens focusing in digital imaging devices
An improved image sensor wherein a first micro-lens array comprised of one or more micro-lenses is positioned over a cavity such that incoming light is focused...
US-7,405,110 Methods of forming implant regions relative to transistor gates
The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed,...
US-7,405,101 CMOS imager with selectively silicided gate
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the...
US-7,405,007 Semiconductor having a substantially uniform layer of electroplated metal
A method of electroplating metal onto a low conductivity layer combines a potential or current reversal waveform with variation in the amplitude and duration of...
US-7,404,719 Contact block and electrical connecting apparatus
A contact block includes a contact having a pair of contact pieces spaced apart, and an electrically insulating combining block for combining the contact pieces....
US-7,404,683 Printer
In a printer, when a cover is closed, a paper issuing path, and a paper setting path are formed downstream from a cutter mechanism in a paper transport path. The...
US-7,404,162 Buffering technique using structured delay skewing
A line buffering technique in which a plurality of line buffers are arranged based on a determined average number of branches and stages that are necessary to...
US-7,404,124 On-chip sampling circuit and method
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers....
US-7,404,071 Memory modules having accurate operating current values stored thereon and methods for fabricating and...
Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance....
US-7,404,066 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,404,033 Method for reading while writing to a single partition flash memory
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient...
US-7,403,631 Electro-acoustic transducer
The two coil spring terminals have the structure of double coil spring terminal including a small diameter coil spring terminal and a large diameter coil spring...
US-7,403,444 Selectable memory word line deactivation
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to...
US-7,403,425 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,403,423 Sensing scheme for low-voltage flash memory
Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their...
US-7,403,419 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,416 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,060 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
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