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Patent # Description
US-7,369,138 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,369,072 Method and apparatus for calibrating imaging device circuits
A method of operating an imaging device, an imaging device, a camera system including an imaging device, and a processing system including an imaging device for...
US-7,368,965 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,368,812 Interposers for chip-scale packages and intermediates thereof
A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal...
US-7,368,810 Invertible microfeature device packages
Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a...
US-7,368,800 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,368,796 Metal gate engineering for surface P-channel devices
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of...
US-7,368,790 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,368,701 Optical channels for multi-level metal optical imagers and method for manufacturing same
The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via....
US-7,368,698 Imaging device with reduced row readout time and method of operating the same
An imager in which a column line bias current control signal is pulsed at some time during and/or after the pulsing of the reset control and the transfer control...
US-7,368,696 Generation and storage of column offsets for a column parallel image sensor
The plural signal chains of an imaging device are calibrated in the digital domain. The pixel array of the imaging device includes a row of calibration pixels....
US-7,368,678 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,368,416 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,368,402 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds
A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,368,399 Methods of forming patterned photoresist layers over semiconductor substrates
This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is...
US-7,368,391 Methods for designing carrier substrates with raised terminals
A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the...
US-7,368,389 Methods of forming electrically conductive plugs
A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An...
US-7,368,382 Atomic layer deposition methods
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a...
US-7,368,381 Methods of forming materials
The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the...
US-7,368,378 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,368,374 Super high density module with integrated wafer level packages
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of...
US-7,368,372 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,368,366 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,368,362 Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,368,344 Methods of reducing floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
US-7,368,343 Low leakage MIM capacitor
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a...
US-7,368,339 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
US-7,368,320 Method of fabricating a two die semiconductor assembly
A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured...
US-7,368,014 Variable temperature deposition methods
A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer...
US-7,367,871 Semiconductor processing methods of removing conductive material
The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a...
US-7,367,845 Modular sockets using flexible interconnects
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,367,343 Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
US-7,367,252 Integrated circuit package separators
An integrated circuit package separator. A base having a plurality of pins extending upwardly therefrom is provided. A support is provided over the base. The...
US-7,366,985 Text based markup language resource interface
A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference...
US-7,366,966 System and method for varying test signal durations and assert times for testing memory devices
A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree...
US-7,366,946 ROM redundancy in ROM embedded DRAM
Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or...
US-7,366,942 Method and apparatus for high-speed input sampling
A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and...
US-7,366,864 Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input...
US-7,366,051 Word line driver circuitry and methods for using the same
Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology,...
US-7,366,045 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary...
US-7,366,041 Input buffer for low voltage operation
An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply...
US-7,366,030 Simultaneous read circuit for multiple memory cells
A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit....
US-7,366,027 Method and apparatus for erasing memory
The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate...
US-7,366,021 Method and apparatus for sensing flash memory using delta sigma modulation
A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a...
US-7,366,017 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
US-7,366,013 Single level cell programming in a multiple level cell non-volatile memory device
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire...
US-7,366,003 Method of operating a complementary bit resistance memory sensor and method of operation
A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one...
US-7,365,901 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,365,829 Method and apparatus for image formation
The present invention relates to a method for adjusting a pattern to be imaged onto a workpiece. The pattern representing an image is divided in a plurality of...
US-7,365,784 Column sample-and-hold cell for CMOS APS sensor
A sample and hold readout circuit and method of operation which minimizes fixed pattern noise during a read out operation. The circuit improves the consistency...
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