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Patent # Description
US-7,404,071 Memory modules having accurate operating current values stored thereon and methods for fabricating and...
Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices to improve system performance....
US-7,404,066 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU...
US-7,404,033 Method for reading while writing to a single partition flash memory
A device manager receives an operation request for a memory device. The device manager suspends interrupts to be serviced and determines if there is sufficient...
US-7,403,631 Electro-acoustic transducer
The two coil spring terminals have the structure of double coil spring terminal including a small diameter coil spring terminal and a large diameter coil spring...
US-7,403,444 Selectable memory word line deactivation
Circuitry and methods allow selected memory word lines (WLs) to be deactivated without using a global deactivate signal. All active WLs do not therefore have to...
US-7,403,425 Programming a flash memory device
An initial verify read operation is performed after each programming pulse. The verify voltage starts at an initial verify voltage for the first word line and...
US-7,403,423 Sensing scheme for low-voltage flash memory
Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their...
US-7,403,419 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,416 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,403,060 Forward biasing protection circuit
A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body...
US-7,403,044 Method of producing balanced data output
Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that...
US-7,403,033 MOS linear region impedance curvature correction
A system and method to correct or cancel MOS linear region impedance curvature employing an analog solution to trim out the MOS linear region impedance curvature...
US-7,402,908 Intermediate semiconductor device structures
A method of forming a metal pattern on a dielectric layer that comprises forming at least one trench in a dielectric layer formed from a photosensitive,...
US-7,402,902 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a...
US-7,402,879 Layered magnetic structures having improved surface planarity for bit material deposition
The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is...
US-7,402,876 Zr-- Sn--Ti--O films
A dielectric film containing Zr--Sn--Ti--O formed by atomic layer deposition using a TiI.sub.4 precursor and a method of fabricating such a dielectric film...
US-7,402,861 Memory cells and select gates of NAND memory arrays
A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric...
US-7,402,850 Back-side trapped non-volatile memory device
Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with...
US-7,402,833 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication
A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD...
US-7,402,789 Methods for pixel binning in an image sensor
Embodiments provide structures and methods for binning pixel signals of a pixel array. Pixel signals for pixels in an element of the array are binned...
US-7,402,533 Masking without photolithography during the formation of a semiconductor device
A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions,...
US-7,402,526 Plasma processing, deposition, and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...
US-7,402,518 Atomic layer deposition methods
A first precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. A second precursor gas different in...
US-7,402,516 Method for making integrated circuits
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,402,512 High aspect ratio contact structure with reduced silicon consumption
A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is...
US-7,402,498 Methods of forming trench isolation regions
The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The...
US-7,402,489 Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the...
A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a...
US-7,402,453 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,402,451 Optimized transistor for imager device
An imager device that has mitigated dark current leakage and punch-through protection. The transistor associated with the photoconversion device is formed with a...
US-7,402,379 Resist exposure system and method of forming a pattern on a resist
A resist exposure system and a method of forming a pattern on a resist are provided and include an exposure source, a photoresist composition, and a mask...
US-7,402,259 Chemical-mechanical polishing methods
A chemical-mechanical polishing (CMP) method includes applying a solid abrasive material to a substrate, polishing the substrate, flocculating at least a portion...
US-7,402,094 Fixed-abrasive chemical-mechanical planarization of titanium nitride
Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The...
US-7,401,267 Program failure recovery
Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array,...
US-7,401,010 Methods of forming radiation-patterning tools; carrier waves and computer readable media
The invention includes a method for placement of sidelobe inhibitors on a radiation-patterning tool. Elements of the tool are represented by design features in a...
US-7,400,549 Memory block reallocation in a flash memory device
A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability....
US-7,400,544 Actively driven V.sub.REF for input buffer noise immunity
A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled...
US-7,400,539 Memory device having terminals for transferring multiple types of data
A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit...
US-7,400,533 Mimicking program verify drain resistance in a memory device
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the...
US-7,400,532 Programming method to reduce gate coupling interference for non-volatile memory
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or...
US-7,400,389 Method and apparatus for testing image sensors
Methods and apparatuses for testing image sensors are disclosed. Desirable apparatuses of the present invention include image sensor testing devices comprising a...
US-7,400,350 System and method for collecting images of a monitored device
A system and method for collecting images of monitored devices, such as utility meters for electricity, gas and water, captures a digital image of a monitored...
US-7,400,124 Apparatus and methods for regulated voltage
An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide...
US-7,400,043 Semiconductor constructions
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid....
US-7,400,032 Module assembly for stacked BGA packages
Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array...
US-7,400,012 Scalable Flash/NV structures and devices with extended endurance
Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of...
US-7,400,004 Isolation structures for preventing photons and carriers from reaching active areas and methods of formation
Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep,...
US-7,399,714 Method of forming a structure over a semiconductor substrate
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the...
US-7,399,671 Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
US-7,399,666 Atomic layer deposition of Zr.sub.3N.sub.4/ZrO.sub.2 films as gate dielectrics
The use of atomic layer deposition (ALD) to form a dielectric layer of zirconium nitride (Zr.sub.3N.sub.4) and zirconium oxide (ZrO.sub.2) and a method of...
US-7,399,657 Ball grid array packages with thermally conductive containers
Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die...
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