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Patent # Description
US-7,370,306 Method and apparatus for designing a pattern on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to...
US-7,370,226 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,370,225 System and method for communicating a software-generated pulse waveform between two servers in a network
A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between...
US-7,370,150 System and method for managing a cache memory
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller....
US-7,370,134 System and method for memory hub-based expansion bus
A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit...
US-7,370,122 Distributed configuration storage
Systems and methods for providing distributed configuration storage are presented. The configuration storage is divided into distributed configuration target...
US-7,369,962 Method and device for data integrity checking
The present invention relates to high speed datapaths, sometimes including mixed digital and analog voltage signals. In particular, it relates to error checking...
US-7,369,623 Apparatuses to simultaneously distribute clock signals and data on integrated circuits, interposers, and...
A technique is described for simultaneously and synchronously transmitting digital data and a clock signal in a digital integrated circuit, circuit board, or...
US-7,369,447 Random cache read
A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the...
US-7,369,436 Vertical NAND flash memory device
Memory devices, arrays, and strings are included that facilitate the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and...
US-7,369,435 Write once read only memory employing floating gates
Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate...
US-7,369,434 Flash memory with multi-bit read
A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory...
US-7,369,379 Methods, circuits, and applications using a resistor and a Schottky diode
A combination of a current limiting resistor and a clamping Schottky diode prevent substantial forward biasing of a pn junction associated with a pad in a...
US-7,369,291 SLM addressing methods and apparatuses
A spatial light modulator may include a plurality of deflectable modulating elements. Each of the deflectable modulating elements may further include a support...
US-7,369,217 Method and device for immersion lithography
The present invention relates to an immersion lithographic system for patterning a work piece arranged at an image plane and covered at least partly with a layer...
US-7,369,168 Circuit for an active pixel sensor
A pixel circuit includes a silicon substrate having a photodiode that converts light intensity into a voltage signal and two metal layers disposed on the...
US-7,369,167 Photo diode ID for CMOS imagers
A CMOS image pixel array formed on a chip is used for storing programmed information within the pixel array. Manufacturing lot and other data is written to the...
US-7,369,138 Full-scene anti-aliasing method and system
A method and system for performing full-scene anti-aliasing for an image through a technique of rotating and unrotating rasterization of a scene and rendering a...
US-7,369,072 Method and apparatus for calibrating imaging device circuits
A method of operating an imaging device, an imaging device, a camera system including an imaging device, and a processing system including an imaging device for...
US-7,368,965 Clock capture in clock synchronization circuitry
Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal,...
US-7,368,812 Interposers for chip-scale packages and intermediates thereof
A carrier substrate, or interposer, for use in a chip-scale package includes a material, such as a semiconductive material, that has a coefficient of thermal...
US-7,368,810 Invertible microfeature device packages
Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a...
US-7,368,800 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,368,796 Metal gate engineering for surface P-channel devices
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of...
US-7,368,790 Strained Si/SiGe/SOI islands and processes of making same
A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An...
US-7,368,701 Optical channels for multi-level metal optical imagers and method for manufacturing same
The manufacture of multi-level optical imagers and the resulting imagers are described. Multiple levels of metallization are prepared, each level having a via....
US-7,368,698 Imaging device with reduced row readout time and method of operating the same
An imager in which a column line bias current control signal is pulsed at some time during and/or after the pulsing of the reset control and the transfer control...
US-7,368,696 Generation and storage of column offsets for a column parallel image sensor
The plural signal chains of an imaging device are calibrated in the digital domain. The pixel array of the imaging device includes a row of calibration pixels....
US-7,368,678 Method for sorting integrated circuit devices
A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including...
US-7,368,416 Methods of removing metal-containing materials
Various methods for selectively etching metal-containing materials (such as, for example, metal nitrides, which can include, for example, titanium nitride)...
US-7,368,402 Systems and methods for forming tantalum oxide layers and tantalum precursor compounds
A method of forming (and apparatus for forming) a tantalum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a...
US-7,368,399 Methods of forming patterned photoresist layers over semiconductor substrates
This invention includes methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a porous antireflective coating is...
US-7,368,391 Methods for designing carrier substrates with raised terminals
A method for designing a carrier substrate includes configuring at least one die-attach location and one or more terminals that protrude from a surface of the...
US-7,368,389 Methods of forming electrically conductive plugs
A method of forming an electrically conductive plug includes providing an opening within electrically insulative material over a node location on a substrate. An...
US-7,368,382 Atomic layer deposition methods
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a...
US-7,368,381 Methods of forming materials
The invention includes methods of forming films over substrates. A substrate is provided within a reaction chamber, and a mixture is also provided within the...
US-7,368,378 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The...
US-7,368,374 Super high density module with integrated wafer level packages
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of...
US-7,368,372 Methods of fabricating multiple sets of field effect transistors
The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative...
US-7,368,366 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,368,362 Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,368,344 Methods of reducing floating body effect
Methods of reducing the floating body effect in vertical transistors are disclosed. The floating body effect occurs when an active region in a pillar is cut off...
US-7,368,343 Low leakage MIM capacitor
Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a...
US-7,368,339 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than...
A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is...
US-7,368,320 Method of fabricating a two die semiconductor assembly
A semiconductor die assembly includes a substantially planar lead frame including a die paddle and a plurality of lead fingers, a first semiconductor die secured...
US-7,368,014 Variable temperature deposition methods
A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer...
US-7,367,871 Semiconductor processing methods of removing conductive material
The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a...
US-7,367,845 Modular sockets using flexible interconnects
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,367,343 Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
US-7,367,252 Integrated circuit package separators
An integrated circuit package separator. A base having a plurality of pins extending upwardly therefrom is provided. A support is provided over the base. The...
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