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Systems and methods for managing endian mode of a device
Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian...
Electronic devices including two or more substrates electrically connected
together and methods of forming such...
Electronic devices may include a first substrate including circuitry components within the substrate, a microscale bond pad on a surface of the substrate, and a...
Memory cells having a self-aligning polarizer
Spin torque transfer memory cells and methods of forming the same are described herein. As an example, spin torque transfer memory cells may include a...
GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
Heating phase change material
A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another...
Cross-point memory utilizing Ru/Si diode
Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium...
Memory cells having heaters with angled sidewalls
Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive...
Memory arrays and methods of forming same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having...
Semiconductor structures and devices including conductive lines and
peripheral conductive pads
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
Methods of forming a non-volatile resistive oxide memory cell and methods
of forming a non-volatile resistive...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal...
Memory arrays with polygonal memory cells having specific sidewall
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines...
Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
Thyristor-based memory cells, devices and systems including the same and
methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
Disabling electrical connections using pass-through 3D interconnects and
associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
Microelectronic devices with through-silicon vias and associated methods
Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten...
Methods of forming silicon-containing dielectric materials and
semiconductor device structures
A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals...
Methods of forming memory cells with air gaps and other low dielectric
Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a...
Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
Switched interface for stacked-die memory architecture with redundancy for
substituting defective memory cells
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request...
Semiconductor device and control method of the same
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of...
Architecture and method for memory programming
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is...
Multiple step programming in a memory device
Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If...
Memory as a programmable logic device
Methods for programming, methods for operating, and memories are disclosed. One such method for programming includes programming a group of memory cells such...
Enhancing nucleation in phase-change memory cells
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime...
Apparatuses and methods for low power current mode sense amplification
Memory apparatuses and methods for low power current mode sense amplification are disclosed. An example memory apparatus may include a current mode sense...
Memory cells, memory cell programming methods, memory cell reading
methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT...
Providing power availability information to memory
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
Memory arrays and methods of forming electrical contacts
Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material...
Systems and methods for memory system management based on thermal
information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
Boot partitions in memory devices and systems
The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of...
Apparatus providing simplified alignment of optical fiber in photonic
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
Probe card and method for manufacturing the same
A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths...
Method and apparatus for enabling a timing synchronization circuit
A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to...
High-input common-mode differential amplifiers
The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and...
Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
Transistors with an extension region having strips of differing
A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions...
Methods and apparatuses including an active area of a tap intersected by a
boundary of a well
Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a...
Methods, structures and devices for increasing memory density
Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different...
Vertical ferroelectric field effect transistor constructions,
constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
Memory cells, arrays of memory cells, and methods of forming memory cells
A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a...
Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
Stacked semiconductor die assemblies with high efficiency thermal paths
and associated systems
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a...
Methods of protecting peripheries of in-process semiconductor wafers and
related in-process wafers and systems
Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material,...
Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a...
Memory systems and memory programming methods
Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of...
Mixed mode programming for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
Device and apparatus having address and command input paths
A device includes a plurality of input terminals, a control circuit, and a plurality of signal buses. Each of the signal buses is coupled between the control...
Program-disturb decoupling for adjacent wordlines of a memory device
Subject matter disclosed herein relates to memory operations regarding programming bits into a memory array.
Low voltage sensing scheme having reduced active power down standby
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier...