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| Patent # | Description |
|---|---|
| US-7,528,440 |
Vertical gain cell A vertical cell is realized. The cell includes a first vertical metal oxide semiconductor (MOS) transistor having a body between a drain region and a source... |
| US-7,528,439 |
Vertical wrap-around-gate field-effect-transistor for high density, low
voltage logic and memory array A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by... |
| US-7,528,435 |
Semiconductor constructions The invention encompasses methods of forming metal nitride proximate dielectric materials. The metal nitride comprises two portions, with one of the portions... |
| US-7,528,430 |
Electronic systems The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second... |
| US-7,528,424 |
Integrated circuitry This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer... |
| US-7,528,401 |
Agglomeration elimination for metal sputter deposition of chalcogenides A method for fabricating chalcogenide materials on substrates, which reduces and/or eliminates agglomeration of materials on the chalcogenide materials; and... |
| US-7,528,064 |
Interconnect structures with bond-pads and methods of forming bump sites
on bond-pads Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example,... |
| US-7,528,043 |
Scalable gate and storage dielectric Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a... |
| US-7,528,037 |
Flash memory having a high-permittivity tunnel dielectric A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages.... |
| US-7,528,007 |
Methods for assembling semiconductor devices and interposers A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that... |
| US-7,527,693 |
Apparatus for improved delivery of metastable species The invention includes a deposition system having a reservoir for containment of a metastable specie connected to a deposition chamber. The system includes a... |
| US-7,527,545 |
Methods and tools for controlling the removal of material from
microfeature workpieces Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method... |
| US-7,526,795 |
Data security for digital data storage A computing system includes data encryption in the data path between a data source and data storage devices. The data storage devices may be local or they may be... |
| US-7,526,713 |
Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The... |
| US-7,526,709 |
Error detection and correction in a CAM An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not... |
| US-7,526,704 |
Testing system and method allowing adjustment of signal transmit timing A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing... |
| US-7,526,095 |
Audio volume control for computer systems A computer system includes an audio chip to generate audio signals at a target volume level to be emitted as audio output by speakers. Also included in the... |
| US-7,525,842 |
Increased NAND flash memory read throughput A method of reading sequential pages of flash memory from alternating memory blocks comprises loading data from a first page into a first primary data cache and... |
| US-7,525,841 |
Programming method for NAND flash A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells... |
| US-7,525,671 |
Registration method and apparatus therefor The present invention relates to a method to determine a position of at least one mark provided on a substrate, comprising the actions of: detecting a first mark... |
| US-7,525,458 |
Method and apparatus for converting parallel data to serial data in high
speed applications A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data... |
| US-7,525,379 |
Low voltage CMOS differential amplifier There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS... |
| US-7,525,354 |
Local coarse delay units Methods, circuits, devices, and systems are provided, including embodiments with local coarse delay units. One embodiment includes generating a first delayed... |
| US-7,525,352 |
Current differential buffer A memory device having a differential buffer is disclosed. In some embodiments, the memory device includes a differential buffer having a differential pair that... |
| US-7,525,332 |
On-chip substrate regulator test mode An on-chip circuit for defect testing with the ability to maintain a substrate voltage at a level more positive or more negative than a normal negative operating... |
| US-7,525,329 |
Electrical connecting apparatus A wiring path of a circuit board has a first vertical path portion penetrating the circuit board at its outer edge in its thickness direction and connected to a... |
| US-7,525,164 |
Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An... |
| US-7,525,149 |
Combined volatile and non-volatile memory device with graded composition
insulator stack A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The... |
| US-7,525,141 |
Memory array with ultra-thin etched pillar surround gate access
transistors and buried data/bit lines A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally... |
| US-7,525,134 |
CMOS imager pixel designs A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are... |
| US-7,524,756 |
Process of forming a semiconductor assembly having a contact structure and
contact liner A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact... |
| US-7,524,410 |
Methods and apparatus for removing conductive material from a
microelectronic substrate A method and apparatus for removing conductive material from a microelectronic substrate is disclosed. One method includes disposing an electrolytic liquid... |
| US-7,523,539 |
Method of manufacturing a probe In a probe manufacturing method, after a metal material for a probe is deposited on a base table, the probe can be detached from the base table relatively easily... |
| US-7,523,400 |
Text based markup language resource interface A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference... |
| US-7,523,381 |
Non-volatile memory with error detection Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated... |
| US-7,522,466 |
DRAM power bus control A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as... |
| US-7,522,341 |
Sharing of microlenses among pixels in image sensors A microlens array having microlenses that correspond to more than one color filter and underlying pixel. In one particular embodiment, each microlens is formed... |
| US-7,521,967 |
Methods of reducing data dependent noise Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may... |
| US-7,521,956 |
Methods and apparatus for adaptively adjusting a data receiver Methods are provided to reduce offsets and timing skews in data signals captured in a data receiver by adaptively adjusting a transition threshold of the data... |
| US-7,521,948 |
Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The... |
| US-7,521,794 |
Intrinsic thermal enhancement for FBGA package A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the... |
| US-7,521,705 |
Reproducible resistance variable insulating memory devices having a shaped
bottom electrode The present invention relates to the use of a shaped bottom electrode in a resistance variable memory device. The shaped bottom electrode ensures that the... |
| US-7,521,378 |
Low temperature process for polysilazane oxidation/densification Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed.... |
| US-7,521,373 |
Compositions for dissolution of low-k dielectric films, and methods of use An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k... |
| US-7,521,371 |
Methods of forming semiconductor constructions having lines In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically... |
| US-7,521,356 |
Atomic layer deposition systems and methods including silicon-containing
tantalum precursor compounds The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): ... |
| US-7,521,355 |
Integrated circuit insulators and related methods A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for... |
| US-7,521,354 |
Low k interlevel dielectric layer fabrication methods A low k interlevel dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide... |
| US-7,521,322 |
Vertical transistors Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to... |
| US-7,521,296 |
Methods of fabricating a microlens including selectively curing flowable,
uncured optically trasmissive material Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material.... |
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