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| Patent # | Description |
|---|---|
| US-7,459,346 |
Intrinsic thermal enhancement for FBGA package A semiconductor device for dissipating heat generated by a die during operation and having a low height profile, a semiconductor die package incorporating the... |
| US-7,459,336 |
Method of forming a chalcogenide material containing device Embodiments of the invention provide a method of forming a chalcogenide material containing device, and particularly resistance variable memory elements. A stack... |
| US-7,458,818 |
Electric connector and electrical connecting apparatus using the same An electrical connecting device is disposed between a circuit board and a probe board opposing each other and used for connection between electrical connection... |
| US-7,458,466 |
Stack processing tray for integrated circuit devices A stack processing tray for use with tray-based integrated circuit device handling systems is disclosed. The stack processing tray has a plurality of cells, each... |
| US-D581,926 |
Storage device |
| US-7,457,997 |
Apparatus and method for detecting over-programming condition in
multistate memory device An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the ... |
| US-7,457,978 |
Adjustable byte lane offset for memory module to reduce skew Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module... |
| US-7,457,912 |
Runtime flash device detection and configuration for flash data management
software A memory device driver is described that can support multiple differing memory devices, in particular, differing Flash memory devices, by being internally... |
| US-7,457,205 |
Linear optical disk changer with side switching capabilities An optical disk changer that is capable of automatically playing both sides of a dual-sided optical disk. By coordinated rotation and delivery of disks taken... |
| US-7,457,184 |
Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site... |
| US-7,457,172 |
Memory device and method having data path with multiple prefetch I/O
configurations A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into... |
| US-7,457,169 |
Flash with consistent latency for read operations A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The... |
| US-7,457,159 |
Integrated DRAM-NVRAM multi-level memory An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate... |
| US-7,457,156 |
NAND flash depletion cell structure NAND architecture Flash memory strings, memory arrays, and memory devices are described that utilize depletion mode floating gate memory cells. Depletion mode... |
| US-7,457,155 |
Non-volatile memory device and method having bit-state assignments
selected to minimize signal coupling A non-volatile memory device programs memory cells in each row in a manner that minimizes the coupling of spurious signals. A control logic unit programs the... |
| US-7,456,928 |
Systems and methods for controlling ambient pressure during processing of
microfeature workpieces, including... Systems and methods for controlling ambient pressure during processing of microfeature workpieces, including during immersion lithography, are disclosed. A... |
| US-7,456,885 |
Per column one-bit ADC for image sensors A per column one-bit analog-to-digital converter for an image sensor. The analog-to-digital converter utilizes the difference between a reference signal current... |
| US-7,456,639 |
Compliant contact structure A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a... |
| US-7,456,504 |
Electronic component assemblies with electrically conductive bonds Improved methods and apparatus are provided for the handling and testing of semiconductor devices. One embodiment comprises a die carrier for one or more... |
| US-7,456,452 |
Light sensor having undulating features for CMOS imager Light sensors in an imager having sloped features including, but not limited to, hemispherical, v-shaped, or other sloped shapes. Light sensors having such a... |
| US-7,456,054 |
Gated lateral thyristor-based random access memory cell (GLTRAM) One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like... |
| US-7,455,956 |
Method to align mask patterns Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming... |
| US-7,455,938 |
Methods of forming patterns in substrates The invention includes methods of forming a pattern in a substrate. A feature location is defined where a square corner is desired to be patterned into the... |
| US-7,455,937 |
Reticles and methods of forming reticles The invention includes reticles and methods of forming reticles. In one aspect, a reticle can include a quartz-containing substrate, an attenuating layer, and an... |
| US-7,455,884 |
Atomic layer deposition with point of use generated reactive gas species A method for atomic layer deposition providing a dispenser unit used to prevent mixing of a precursor gas and an input gas. From the dispenser unit a flow of the... |
| US-D581,413 |
Storage device with slide |
| US-7,454,671 |
Memory device testing system and method having real time redundancy repair
analysis A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read... |
| US-7,454,646 |
Efficient clocking scheme for ultra high-speed systems There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original... |
| US-7,454,593 |
Row and column enable signal activation of processing array elements with
interconnection logic to simulate bus... The present invention relates to the control of an array of processing elements in a parallel processor using row and column select lines. For each column in the... |
| US-7,454,558 |
Non-volatile memory with erase block state indication in data section An improved Flash memory device with a distributed erase block management (EBM) scheme is detailed that enhances operation and helps minimize write fatigue of... |
| US-7,454,549 |
Systems and methods for performing a hot input function A computer software system is disclosed for facilitating a user's replacement or insertion of devices in a computer server network system. The system allows a... |
| US-7,454,451 |
Method for finding local extrema of a set of values for a parallel
processing element A method for finding a local extrema for a single processing element having a set of values associated therewith includes separating the set of values into an... |
| US-7,453,751 |
Sample and hold memory sense amplifier A memory sense amplifier includes a sample and hold circuit followed by a differential amplifier. The sample and hold circuit samples a reference voltage on a... |
| US-7,453,746 |
Reconstruction of signal timing in integrated circuits Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of... |
| US-7,453,737 |
Program method with optimized voltage level for flash memory A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the... |
| US-7,453,723 |
Memory with weighted multi-page read A memory device is described that provides increased output data to help evaluate data errors from bit line coupling and floating gate coupling during a read... |
| US-7,453,718 |
Digital data apparatuses and digital data operational methods Digital data apparatuses and digital data operational methods are described. According to one embodiment, a digital data apparatus includes a semiconductive... |
| US-7,453,152 |
Device having reduced chemical mechanical planarization The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a... |
| US-7,453,134 |
Integrated circuit device with a circuit element formed on an active
region having rounded corners An integrated circuit device has a substrate with first and second portions. One or more first active regions are formed in the first portion of the substrate.... |
| US-7,453,115 |
Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site... |
| US-7,453,112 |
Integrated circuit memory cells and methods of forming An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor... |
| US-7,453,103 |
Semiconductor constructions The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the... |
| US-7,453,082 |
Small electrode for a chalcogenide switching device and method for
fabricating same A memory cell and a method of fabricating the memory cell having a small active area are provided. By forming a spacer in a window that is sized at the... |
| US-7,452,816 |
Semiconductor processing method and chemical mechanical polishing methods This invention includes a chemical mechanical polishing method including providing a substrate having an organic material to be polished by chemical mechanical... |
| US-7,452,770 |
Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell... |
| US-7,452,766 |
Finned memory cells and the fabrication thereof Methods and apparatus are provided. For an embodiment, a plurality fins is formed in a substrate so that the fins protrude from a substrate. After the plurality... |
| US-7,452,760 |
Thin film transistors and semiconductor constructions A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a... |
| US-7,452,759 |
Carbon nanotube field effect transistor and methods for making same A structure and fabrication process for a carbon nanotube field effect transistor is disclosed herein. In one embodiment, a method for forming a carbon nanotube... |
| US-7,452,732 |
Comparing identifying indicia formed using laser marking techniques to an
identifying indicia model A laser marking apparatus and method for marking the surface of a semiconductor chip are described herein. A laser beam is directed to a location on the surface... |
| US-7,451,533 |
NC automatic lathe An NC automatic lathe including abase board, a headstock provided with a main spindle and so arranged as to move in a direction of Z1 axis, a back attachment... |
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