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| Patent # | Description |
|---|---|
| US-7,413,962 |
Method for forming sublithographic features during the manufacture of a
semiconductor device and a resulting... A method for forming a semiconductor device comprises forming a layer to be etched, then forming a hard mask layer over the layer to be etched. The hard mask is... |
| US-7,413,952 |
Methods of forming a plurality of circuit components and methods of
forming a plurality of structures suspended... A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is... |
| US-7,413,948 |
Semiconductor capacitor structure and method to form same A semiconductor capacitor structure comprising sidewalls of conductive hemispherical grained material, a base of metal silicide material, and a metal nitride... |
| US-7,413,946 |
Formation of standard voltage threshold and low voltage threshold MOSFET
devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first... |
| US-7,413,928 |
Die-wafer package and method of fabricating same A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a... |
| US-7,413,500 |
Methods for planarizing workpieces, e.g., microelectronic workpieces This disclosure provides methods and apparatus for predictably changing the thickness of a microfeature workpiece. One implementation provides a planarizing... |
| US-7,413,480 |
Silicon pillars for vertical transistors In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In... |
| US-7,413,342 |
DRAM temperature measurement system A converter comprising a comparator having a first input operable to receive a first signal, a second input operable to receive a second signal, and an output, a... |
| US-7,412,634 |
On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers.... |
| US-7,412,574 |
System and method for arbitration of memory responses in a hub-based
memory system A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory... |
| US-7,412,571 |
Memory arbitration system and method having an arbitration packet protocol A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub.... |
| US-7,412,566 |
Memory hub and access method having internal prefetch buffers A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests... |
| US-7,411,857 |
Power savings in active standby mode Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be... |
| US-7,411,848 |
Independent polling for multi-page programming A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the... |
| US-7,411,832 |
Programming a non-volatile memory device A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial... |
| US-7,411,823 |
In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory... |
| US-7,411,812 |
Memory architecture and method of manufacture and operation thereof An architecture, and its method of formation and operation, containing a high density memory array of semi-volatile or non-volatile memory elements, including,... |
| US-7,411,807 |
System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled... |
| US-7,411,651 |
PSM alignment method and device The present invention relates to alignment of a writing system and a workpiece. In particular, it relates to alignment to write a second layer pattern on a... |
| US-7,411,621 |
Apparatus and method for eliminating artifacts in active pixel sensor
(APS) imagers An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a... |
| US-7,411,566 |
System and method for a portable terminal having a dual display module
structure A portable terminal has the dual display module structure in which a plurality of panels provided in the portable terminal are combined with clear conjunction to... |
| US-7,411,304 |
Semiconductor interconnect having conductive spring contacts An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage... |
| US-7,411,300 |
Agglomeration control using early transition metal alloys Structures and methods of fabricating portions of integrated circuit devices to reduce agglomeration tendencies of high surface-energy metals used in... |
| US-7,411,297 |
Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The... |
| US-7,411,286 |
Methods for stacking wire-bonded integrated circuit dice on flip-chip
bonded integrated circuit dice An inventive electronic device, such as a multi-chip module (MCM), a Single In-line Memory Module (SIMM), or a Dual In-line Memory Module (DIMM), includes a... |
| US-7,411,262 |
Self-aligned, low-resistance, efficient memory array The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed... |
| US-7,411,255 |
Dopant barrier for doped glass in memory devices A semiconductor device has a diffusion barrier formed between a doped glass layer and surface structures formed on a substrate. The diffusion barrier includes... |
| US-7,411,254 |
Semiconductor substrate The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a... |
| US-7,411,237 |
Lanthanum hafnium oxide dielectrics Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers,... |
| US-7,410,918 |
Systems and methods for forming metal oxides using alcohols A method of forming (and an apparatus for forming) a metal oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a... |
| US-7,410,917 |
Atomic layer deposited Zr-Sn-Ti-O films using TiI.sub.4 Various structures having a dielectric film containing Zr--Sn--Ti--O formed by atomic layer deposition using a TiI.sub.4 precursor and a method of fabricating... |
| US-7,410,911 |
Method for stabilizing high pressure oxidation of a semiconductor device A method and apparatus for preventing N.sub.2O from becoming super critical during a high pressure oxidation stage within a high pressure oxidation furnace are... |
| US-7,410,910 |
Lanthanum aluminum oxynitride dielectric films Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of... |
| US-7,410,903 |
Methods of patterning substrates The invention includes a template comprising one or both of CdS and CdSe adhered to a base in a desired pattern. The base can be any transparent or translucent... |
| US-7,410,898 |
Methods of fabricating interconnects for semiconductor components In one aspect, the invention encompasses a method of fabricating an interconnect for a semiconductor component. A semiconductor substrate is provided, and an... |
| US-7,410,867 |
Vertical transistor with horizontal gate layers Vertical body transistors with adjacent horizontal gate layers are used to form a memory array in a high density flash electrically erasable and programmable... |
| US-7,410,863 |
Methods of forming and using memory cell structures A method of filling vias for a PCRAM cell with a metal is described. A PCRAM intermediate structure including a substrate, a first conductor, and an insulator... |
| US-7,410,856 |
Methods of forming vertical transistors A vertical transistor forming method includes forming a first pillar above a first source/drain and between second and third pillars, providing a first recess... |
| US-7,410,748 |
Method of etching materials patterned with a single layer 193nm resist A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom... |
| US-7,410,668 |
Methods, systems, and apparatus for uniform chemical-vapor depositions Integrated circuits, the key components in thousands of electronic and computer products, are generally built layer by layer on a silicon substrate. One common... |
| US-7,409,762 |
Method for fabricating an interconnect for semiconductor components A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on... |
| US-7,409,529 |
Method and apparatus for a shift register based interconnection for a
massively parallel processor array A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the... |
| US-7,409,493 |
Top/bottom symmetrical protection scheme for flash A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The... |
| US-7,408,828 |
System and method for reducing power consumption during extended refresh
periods of dynamic random access... A dynamic random access memory ("DRAM") device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate... |
| US-7,408,825 |
Apparatus and method for repairing a semiconductor memory An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit... |
| US-7,408,822 |
Alignment of memory read data and clocking Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To... |
| US-7,408,814 |
Method and apparatus for filtering output data Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a... |
| US-7,408,813 |
Block erase for volatile memory A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a... |
| US-7,408,810 |
Minimizing effects of program disturb in a memory device A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the... |
| US-7,408,808 |
User configurable commands for flash memory A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of... |
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