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| Patent # | Description |
|---|---|
| US-7,364,997 |
Methods of forming integrated circuitry and methods of forming local
interconnects In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive... |
| US-7,364,985 |
Method for creating electrical pathways for semiconductor device
structures using laser machining processes A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention... |
| US-7,364,981 |
Methods of forming trench isolation in the fabrication of integrated
circuitry, methods of fabricating memory... The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including... |
| US-7,364,966 |
Method for forming a buried digit line with self aligning spacing layer
and contact plugs during the formation... A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line... |
| US-7,364,934 |
Microelectronic imaging units and methods of manufacturing microelectronic
imaging units Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one... |
| US-7,364,644 |
Silver selenide film stoichiometry and morphology control in sputter
deposition A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The... |
| US-7,363,694 |
Method of testing using compliant contact structures, contactor cards and
test system A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a... |
| US-7,363,452 |
Pipelined burst memory access A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to... |
| US-7,363,419 |
Method and system for terminating write commands in a hub-based memory
system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write... |
| US-7,362,641 |
Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data... |
| US-7,362,637 |
Current switching sensor detector A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current... |
| US-7,362,634 |
Built-in system and method for testing integrated circuit timing
parameters A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus... |
| US-7,362,627 |
Method and apparatus for synchronizing data from memory arrays According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for... |
| US-7,362,619 |
Data strobe synchronization circuit and method for double data rate,
multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control... |
| US-7,362,611 |
Non-volatile memory copy back Data move operations in a memory device are described that enable identification of data errors. During a write operation, identified errors are flagged and used... |
| US-7,362,113 |
Universal wafer carrier for wafer level die burn-in A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer... |
| US-7,362,111 |
Device for evaluating at least one electrical conducting structure of an
electronic component An apparatus and method for evaluating the integrity of each contact pin of an electronic component having multiple contact pins. In one embodiment, the... |
| US-7,361,928 |
Doped aluminum oxide dielectrics Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation... |
| US-7,361,862 |
Laser marking system for dice carried in trays and method of operation A laser marking system for IC packages including a tray input shuttle assembly and a tray transport borne by a transport actuator for moving a tray carrier... |
| US-7,361,614 |
Method of depositing a silicon dioxide comprising layer in the fabrication
of integrated circuitry This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench... |
| US-7,361,596 |
Semiconductor processing methods The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of... |
| US-7,361,569 |
Methods for increasing photo-alignment margins Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory... |
| US-7,361,559 |
Manufacturing method for a MOS transistor comprising layered relaxed and
strained SiGe layers as a channel region The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile... |
| US-7,361,234 |
Photolithographic stepper and/or scanner machines including cleaning
devices and methods of cleaning... Stepper and/or scanner machines including cleaning devices and methods for cleaning stepper and/or scanner machines are disclosed herein. In one embodiment, a... |
| US-7,361,152 |
Corrugated mattress vibrator longitudinally vibrated A mattress vibrator comprises a mat having a hard plate and an elastic plate which are laminated on each other, and the mat is provided with a vibration... |
| US-7,361,078 |
Subpad support with releasable subpad securing element and polishing
apparatus A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad... |
| US-D567,217 |
Earphone |
| US-7,360,011 |
Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system... |
| US-7,360,006 |
Apparatus and method for managing voltage buses The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply... |
| US-7,359,607 |
Waveguide for thermo optic device A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the... |
| US-7,359,258 |
Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section... |
| US-7,359,243 |
Memory cell repair using fuse programming method in a flash memory device A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of... |
| US-7,359,241 |
In-service reconfigurable DRAM and flash memory device A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory... |
| US-7,358,872 |
Method and apparatus for converting parallel data to serial data in high
speed applications A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline... |
| US-7,358,751 |
Contact pin assembly and contactor card A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a... |
| US-7,358,596 |
Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly... |
| US-7,358,587 |
Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop... |
| US-7,358,568 |
Low resistance semiconductor process and structures A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an... |
| US-7,358,562 |
NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is... |
| US-7,358,561 |
Source lines for NAND memory devices A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first... |
| US-7,358,554 |
Semiconductor manufacturing apparatus for modifying-in-film stress of thin
films, and product formed thereby An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on... |
| US-7,358,553 |
System and method for reducing shorting in memory cells An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce... |
| US-7,358,517 |
Method and apparatus for imager quality testing An apparatus and method of detecting a defect in an imager die package. The method comprises the steps of exposing the imager die package to light at a first... |
| US-7,358,188 |
Method of forming conductive metal silicides by reaction of metal with
silicon The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a... |
| US-7,358,185 |
Device having contact pad with a conductive layer and a conductive
passivation layer A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material... |
| US-7,358,178 |
Semiconductor substrates including I/O redistribution using wire bonds and
anisotropically conductive film,... Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of... |
| US-7,358,171 |
Method to chemically remove metal impurities from polycide gate sidewalls An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a... |
| US-7,358,170 |
Methods of forming conductive interconnects, and methods of depositing
nickel The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The... |
| US-7,358,161 |
Methods of forming transistor devices associated with
semiconductor-on-insulator constructions The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a ... |
| US-7,358,154 |
Method for fabricating packaged die Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The... |
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