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Patent # Description
US-7,361,614 Method of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry
This invention includes methods of depositing a silicon dioxide comprising layer in the fabrication of integrated circuitry, and to methods of forming trench...
US-7,361,596 Semiconductor processing methods
The invention includes methods of forming titanium-containing materials, such as, for example, titanium silicide. The invention can use alternating cycles of...
US-7,361,569 Methods for increasing photo-alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory...
US-7,361,559 Manufacturing method for a MOS transistor comprising layered relaxed and strained SiGe layers as a channel region
The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile...
US-7,361,234 Photolithographic stepper and/or scanner machines including cleaning devices and methods of cleaning...
Stepper and/or scanner machines including cleaning devices and methods for cleaning stepper and/or scanner machines are disclosed herein. In one embodiment, a...
US-7,361,152 Corrugated mattress vibrator longitudinally vibrated
A mattress vibrator comprises a mat having a hard plate and an elastic plate which are laminated on each other, and the mat is provided with a vibration...
US-7,361,078 Subpad support with releasable subpad securing element and polishing apparatus
A subpad support for use in a web format or belt format polishing apparatus for polishing one or more layers of semiconductor device structures. The subpad...
US-D567,217 Earphone
US-7,360,011 Memory hub and method for memory system performance monitoring
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,360,006 Apparatus and method for managing voltage buses
The present technique relates to a method and apparatus for managing voltage buses. In a memory device, such as SRAM or DRAM, a periphery voltage bus may supply...
US-7,359,607 Waveguide for thermo optic device
A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the...
US-7,359,258 Semiconductor memory with wordline timing
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section...
US-7,359,243 Memory cell repair using fuse programming method in a flash memory device
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of...
US-7,359,241 In-service reconfigurable DRAM and flash memory device
A memory cell that has both a DRAM cell and a non-volatile memory cell. The non-volatile memory cell might include a flash memory or an NROM cell. The memory...
US-7,358,872 Method and apparatus for converting parallel data to serial data in high speed applications
A method and apparatus to convert parallel data to serial data. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline...
US-7,358,751 Contact pin assembly and contactor card
A compliant contact pin assembly and a contactor card system are provided. The compliant contact pin assembly includes a contact pin formed from a portion of a...
US-7,358,596 Device isolation for semiconductor devices
Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly...
US-7,358,587 Semiconductor structures
In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop...
US-7,358,568 Low resistance semiconductor process and structures
A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an...
US-7,358,562 NROM flash memory devices on ultrathin silicon
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is...
US-7,358,561 Source lines for NAND memory devices
A NAND memory device has a source line connected to two or more columns of serially-connected floating-gate transistors. The source line includes a first...
US-7,358,554 Semiconductor manufacturing apparatus for modifying-in-film stress of thin films, and product formed thereby
An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on...
US-7,358,553 System and method for reducing shorting in memory cells
An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce...
US-7,358,517 Method and apparatus for imager quality testing
An apparatus and method of detecting a defect in an imager die package. The method comprises the steps of exposing the imager die package to light at a first...
US-7,358,188 Method of forming conductive metal silicides by reaction of metal with silicon
The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a...
US-7,358,185 Device having contact pad with a conductive layer and a conductive passivation layer
A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material...
US-7,358,178 Semiconductor substrates including I/O redistribution using wire bonds and anisotropically conductive film,...
Methods and apparatus for eliminating wire sweep and shorting while avoiding the use of under-bump metallization and high cost attendant to the use of...
US-7,358,171 Method to chemically remove metal impurities from polycide gate sidewalls
An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a...
US-7,358,170 Methods of forming conductive interconnects, and methods of depositing nickel
The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The...
US-7,358,161 Methods of forming transistor devices associated with semiconductor-on-insulator constructions
The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a ...
US-7,358,154 Method for fabricating packaged die
Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The...
US-7,358,146 Method of forming a capacitor
A carbon containing masking layer is patterned to include a plurality of container openings therein having minimum feature dimensions of less than or equal to...
US-7,358,139 Method of forming a field effect transistor including depositing and removing insulative material effective to...
The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising...
US-7,358,131 Methods of forming SRAM constructions
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
US-7,358,117 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
US-7,358,103 Method of fabricating an imaging device for collecting photons
A photon collector has a reflecting metal layer to increase photon collection efficiency in a solid state imaging sensor. The reflecting metal layer reflects...
US-7,357,695 Systems and methods for mechanical and/or chemical-mechanical polishing of microfeature workpieces
Systems and methods for polishing microfeature workpieces. In one embodiment, a method includes determining a status of a characteristic of a microfeature...
US-D566,709 Storage device
US-7,356,723 Method and apparatus for data transfer
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the...
US-7,355,922 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,355,920 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,355,894 Programming flash memories
A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control...
US-7,355,464 Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency
A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows...
US-7,355,423 Method for optimizing probe card design
A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit...
US-7,355,387 System and method for testing integrated circuit timing margins
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,355,273 Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods
An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and...
US-7,355,267 Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of...
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,355,244 Electrical devices with multi-walled recesses
The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate...
US-7,355,232 Memory devices with dual-sided capacitors
A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of...
US-7,355,231 Memory circuitry with oxygen diffusion barrier layer received over a well base
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
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