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Patent # Description
US-7,368,014 Variable temperature deposition methods
A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer...
US-7,367,871 Semiconductor processing methods of removing conductive material
The invention includes a semiconductive processing method of electrochemical-mechanical removing at least some of a conductive material from over a surface of a...
US-7,367,845 Modular sockets using flexible interconnects
A modular bare die socket assembly is provided for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a...
US-7,367,343 Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
US-7,367,252 Integrated circuit package separators
An integrated circuit package separator. A base having a plurality of pins extending upwardly therefrom is provided. A support is provided over the base. The...
US-7,366,985 Text based markup language resource interface
A software control method and apparatus for displaying a text based markup language interface. The interface can interact with a computer to provide reference...
US-7,366,966 System and method for varying test signal durations and assert times for testing memory devices
A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree...
US-7,366,946 ROM redundancy in ROM embedded DRAM
Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or...
US-7,366,942 Method and apparatus for high-speed input sampling
A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and...
US-7,366,864 Memory hub architecture having programmable lane widths
A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input...
US-7,366,051 Word line driver circuitry and methods for using the same
Word line driver circuitry for selectively charging and discharging one or more word lines is provided. The driver circuitry uses a dual transistor topology,...
US-7,366,045 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
A resistive memory device requires a power supply having a reduced number of voltage taps and reduced power consumption. In accordance with one exemplary...
US-7,366,041 Input buffer for low voltage operation
An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply...
US-7,366,030 Simultaneous read circuit for multiple memory cells
A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit....
US-7,366,027 Method and apparatus for erasing memory
The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate...
US-7,366,021 Method and apparatus for sensing flash memory using delta sigma modulation
A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a...
US-7,366,017 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
US-7,366,013 Single level cell programming in a multiple level cell non-volatile memory device
A multiple level cell memory array has an area that can be programmed as single level cells. The cells to be programmed are initially programmed with the desire...
US-7,366,003 Method of operating a complementary bit resistance memory sensor and method of operation
A method and apparatus are disclosed for sensing the resistance state of a resistance-based memory element using complementary resistance-based elements, one...
US-7,365,901 Pattern generator
The present invention relates to an apparatus for creating a pattern on a workpiece sensitive to radiation, such as a photomask a display panel or a microoptical...
US-7,365,829 Method and apparatus for image formation
The present invention relates to a method for adjusting a pattern to be imaged onto a workpiece. The pattern representing an image is divided in a plurality of...
US-7,365,784 Column sample-and-hold cell for CMOS APS sensor
A sample and hold readout circuit and method of operation which minimizes fixed pattern noise during a read out operation. The circuit improves the consistency...
US-7,365,773 CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics
An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel...
US-7,365,597 Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy
A switched capacitor CMOS amplifier uses a first stage non-inverting CMOS amplifier driving a second stage inverting CMOS amplifier. The first stage amplifier is...
US-7,365,570 Pseudo-differential output driver with high immunity to noise and jitter
Circuits and methods are provided for transmitting a pseudo-differential output signal with relatively high immunity to noise and jitter. The output driver of...
US-7,365,558 In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays
A burn-in board for burn-in and electrical testing of a plurality of integrated circuit devices that is disposed in one or more processing trays may include a...
US-7,365,424 Microelectronic component assemblies with recessed wire bonds and methods of making same
The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one...
US-7,365,420 Semiconductor packages and methods for making and using same
A semiconductor package is provided which includes a substrate having a plurality of semiconductor dice mounted thereon. The substrate is divided into segments...
US-7,365,411 Resistance variable memory with temperature tolerant materials
A PCRAM memory device having a chalcogenide glass layer, preferably comprising antimony selenide having a stoichiometric formula of about Sb.sub.2Se.sub.3, and a...
US-7,365,409 Two-transistor pixel with buried reset channel and method of formation
A two-transistor pixel of an imager has a reset region formed adjacent a charge collection region of a photodiode and in electrical communication with a gate of...
US-7,365,388 Embedded trap direct tunnel non-volatile memory
The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over...
US-7,365,385 DRAM layout with vertical FETs and method of formation
DRAM cell arrays having a cell area of less than about 4F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate...
US-7,365,384 Trench buried bit line memory devices and methods thereof
A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed...
US-7,365,305 Layered lens structures and methods of production in which radius of curvature of the upper lens can be varied
A microlens structure includes lower lens layers on a substrate. A sputtered layer of glass, such as silicon oxide, is applied over the lower lens layers at an...
US-7,365,028 Methods of forming metal oxide and semimetal oxide
The invention includes methods of forming metal oxide and/or semimetal oxide. The invention can include formation of at least one metal-and-halogen-containing...
US-7,365,027 ALD of amorphous lanthanide doped TiO.sub.x films
The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiO.sub.x) doped with lanthanide elements, such as samarium,...
US-7,364,997 Methods of forming integrated circuitry and methods of forming local interconnects
In one implementation, field oxide is grown within bulk semiconductive material in a first circuitry area and not over immediately adjacent bulk semiconductive...
US-7,364,985 Method for creating electrical pathways for semiconductor device structures using laser machining processes
A method for creating electrical pathways for semiconductor device structures using laser machining processes is provided. The method of the present invention...
US-7,364,981 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory...
The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including...
US-7,364,966 Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation...
A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line...
US-7,364,934 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one...
US-7,364,644 Silver selenide film stoichiometry and morphology control in sputter deposition
A method of sputter depositing silver selenide and controlling the stoichiometry and nodular defect formations of a sputter deposited silver-selenide film. The...
US-7,363,694 Method of testing using compliant contact structures, contactor cards and test system
A compliant contact structure and contactor card for operably coupling with a semiconductor device to be tested includes a substantially planar substrate with a...
US-7,363,452 Pipelined burst memory access
A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to...
US-7,363,419 Method and system for terminating write commands in a hub-based memory system
A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write...
US-7,362,641 Method and system for low power refresh of dynamic random access memories
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data...
US-7,362,637 Current switching sensor detector
A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current...
US-7,362,634 Built-in system and method for testing integrated circuit timing parameters
A built-in self-test system for a dynamic random access memory device using a data output register of the memory device to apply test signals to data bus...
US-7,362,627 Method and apparatus for synchronizing data from memory arrays
According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for...
US-7,362,619 Data strobe synchronization circuit and method for double data rate, multi-bit writes
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control...
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