Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,350,093 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
US-7,350,044 Data move method and apparatus
An improved Flash memory device, control circuit, or data handling methods is described that facilitate the moving and consolidating data in split and non-split...
US-7,350,018 Method and system for using dynamic random access memory as cache memory
A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity...
US-7,349,277 Method and system for reducing the peak current in refreshing dynamic random access memory devices
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the...
US-7,349,273 Access circuit and method for allowing external test voltage to be applied to isolated wells
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are...
US-7,349,270 Semiconductor memory with wordline timing
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section...
US-7,349,269 Programmable DQS preamble
A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where...
US-7,349,252 Integrated DRAM-NVRAM multi-level memory
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate...
US-7,349,232 6F.sup.2 DRAM cell design with 3F-pitch folded digitline sense amplifier
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a...
US-7,348,674 Low capacitance wiring layout
Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated...
US-7,348,671 Vias having varying diameters and fills for use with a semiconductor device and methods of forming...
A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second...
US-7,348,652 Bulk-isolated PN diode and method of forming a bulk-isolated PN diode
A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another...
US-7,348,613 CMOS imager with selectively silicided gates
The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the...
US-7,348,238 Bottom electrode for memory device and method of forming the same
Contacts having use in an integrated circuit and exemplary methods of forming the contacts are disclosed. The methods involve forming a conductive cap over a...
US-7,348,237 NOR flash memory cell with high storage density
Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor...
US-7,348,236 Formation of memory cells and select gates of NAND memory arrays
Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing...
US-7,348,234 Methods of forming capacitor constructions
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,348,215 Methods for assembly and packaging of flip chip configured dice with interposer
A method for assembly and packaging of one or more flip chip-configured semiconductor dice with an interposer substrate to form a flip chip-type semiconductor...
US-7,348,213 Method for forming component mounting hole in semiconductor substrate
The present invention provides to a substrate for a semiconductor device, in which electric characteristics to high-speed signals are enhanced by facilitating...
US-7,348,209 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,348,205 Method of forming resistance variable devices
A method of forming a resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising...
US-7,347,767 Retaining rings, and associated planarizing apparatuses, and related methods for planarizing micro-device...
Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head...
US-7,347,349 Apparatus and method for printing micro metal structures
A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using...
US-7,347,348 Apparatus and method for depositing and reflowing solder paste on a microelectronic workpiece
Stenciling machines and methods for forming solder balls on microelectronic workpieces are disclosed herein. In one embodiment, a method for depositing and...
US-7,346,818 Method and apparatus for redundant location addressing using data compression
A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to...
US-7,346,817 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems
A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal...
US-7,346,182 Electroacoustic transducer and method for manufacturing the same
A diaphragm subassembly comprises a voice coil, a diaphragm, a frame, and a pair of terminal members. A magnetic circuit unit comprises a yoke, a magnet, and a...
US-7,346,162 Public key cryptography using matrices
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private...
US-7,345,937 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,345,932 Low power dissipation voltage generator
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a...
US-7,345,924 Programming memory devices
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether...
US-7,345,922 Position based erase verification levels in a flash memory device
The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to...
US-7,345,918 Selective threshold voltage verification and compaction
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of...
US-7,345,575 Radio frequency data communications device with adjustable receiver sensitivity and method
A device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving circuitry provided on the monolithic integrated...
US-7,345,515 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,345,358 Copper interconnect for semiconductor device
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,345,350 Process and integration scheme for fabricating conductive components, through-vias and semiconductor components...
A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an...
US-7,345,333 Double sided container process used during the manufacture of a semiconductor device
A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact...
US-7,345,332 Semiconductor constructions
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and...
US-7,345,299 Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon...
The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile...
US-7,345,269 Method and apparatus providing configurable current source device for image sensors with a selective current at...
A configurable current source for imager readout system that can be operated as a simple-current-source or as a cascode-current-source. The configurable current...
US-7,344,977 Method of electroplating a substance over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,344,975 Method to reduce charge buildup during high aspect ratio contact etch
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer...
US-7,344,969 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted...
US-7,344,948 Methods of forming transistors
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
US-7,344,946 Structure for amorphous carbon based non-volatile memory
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a...
US-7,344,942 Isolation regions for semiconductor devices and their formation
A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas...
US-7,344,937 Methods and apparatus with silicide on conductive structures
Exemplary embodiments of the invention provide pixel circuits having transistors with silicide on top of their gate stacks. In the exemplary embodiments,...
US-7,344,921 Integrated circuit device having reduced bow and method for making same
An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of...
US-7,344,899 Die assembly and method for forming a die on a wafer
A method for forming a die on a wafer is provided. The method includes forming on a wafer a die having an active portion that includes integrated circuitry. The...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.