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Patent # Description
US-7,338,609 Partial edge bead removal to allow improved grounding during e-beam mask writing
A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask...
US-RE40,137 Methods for forming integrated circuits within substrates
.[.The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of...
US-7,337,404 Graphical representation of system information on a remote computer
A method and apparatus for gathering system information into a file and transmitting the file to a remote location for presentation as a graphical display. A...
US-7,337,088 Intelligent measurement modular semiconductor parametric test system
An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate...
US-7,336,548 Clock generating circuit with multiple modes of operation
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock...
US-7,336,547 Memory device having conditioning output data
A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data....
US-7,336,541 NAND flash memory cell programming
A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable...
US-7,336,537 Handling defective memory blocks of NAND memory devices
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the...
US-7,336,536 Handling defective memory blocks of NAND memory devices
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the...
US-7,336,531 Multiple level cell memory device with single bit per cell, re-mappable memory block
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode...
US-7,336,522 Apparatus and method to reduce undesirable effects caused by a fault in a memory device
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage...
US-7,336,430 Extended depth of field using a multi-focal length lens with a controlled range of spherical aberration and a...
An extended depth of field is achieved by a computational imaging system that combines a multifocal imaging subsystem for producing a purposefully blurred...
US-7,336,111 Fast-locking digital phase locked loop
An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization...
US-7,336,106 Phase detector and method having hysteresis characteristics
A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector...
US-7,336,084 Delay lock circuit having self-calibrating loop
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement...
US-7,335,994 Semiconductor component having multiple stacked dice
A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for...
US-7,335,988 Use of palladium in IC manufacturing with conductive polymer bump
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible...
US-7,335,985 Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
US-7,335,981 Methods for creating electrophoretically insulated vias in semiconductive substrates
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,335,978 Semiconductor component having stiffener, circuit decal and terminal contacts
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
US-7,335,968 High permeability composite films to reduce noise in high speed interconnects
A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first...
US-7,335,965 Packaging of electronic chips with air-bridge structures
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly...
US-7,335,963 Light block for pixel arrays
Imager devices are formed with light block material between microlenses to enhance the characteristics of image acquisition. The light block material may be...
US-7,335,962 Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
US-7,335,958 Tailoring gate work-function in image sensors
Embodiments of the invention provide a method of forming a pixel cell and the resultant pixel cell a photo-conversion device formed at a surface of a substrate...
US-7,335,935 Semiconductor structures
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be...
US-7,335,571 Method of making a semiconductor device having an opening in a solder mask
A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior...
US-7,335,533 Methods for assembling semiconductor devices in superimposed relation with adhesive material defining the...
A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a...
US-7,335,525 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,335,396 Methods for controlling mass flow rates and pressures in passageways coupled to reaction chambers and systems...
Methods, apparatuses, and systems for controlling mass flow rates and pressures in passageways coupled to reaction chambers are disclosed herein. In one...
US-RE40,114 Tungsten silicide (WSIX) deposition process for semiconductor manufacture
A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the...
US-7,333,908 Techniques for generating test patterns in high speed memory devices
A system and methods for calibrating a memory device are provided. More specifically, a technique for internally generating a test pattern within a memory device...
US-7,333,674 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
US-7,333,520 Apparatus for multiplexing signals through I/O pins
One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor...
US-7,333,384 Techniques for storing accurate operating current values
Methods of configuring a system. More specifically, operating current values corresponding to respective memory devices of memory module may be stored in...
US-7,333,370 Method to prevent bit line capacitive coupling
Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well...
US-7,333,366 Common wordline flash array architecture
The memory area on a die required for row (X) and column (Y) decoders is reduced by a plurality of memory array blocks sharing wordlines to a single row decoder....
US-7,333,355 Techniques for implementing accurate operating current values stored in a database
Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on...
US-7,333,267 Micro-lenses for CMOS imagers
A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate an lens material located within the substrate, the substrate...
US-7,333,145 Camera module
A camera module comprising an image sensor array, a gain amplifier, an indicator set to indicate whether a first flash device or a second flash device is...
US-7,332,950 DLL measure initialization circuit for high frequency operation
A memory device, delay lock loop circuit (DLL) and DLL reset circuitry are described. The DLL includes a shift register and a measured delay for pre-loading the...
US-7,332,946 Power supply voltage detection circuitry and methods for use of the same
Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus...
US-7,332,820 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted...
US-7,332,819 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, are provided which have at least two semiconductor dies disposed on a substrate in a stacked arrangement, the...
US-7,332,811 Integrated circuit interconnect
A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline...
US-7,332,790 Semiconductor device having an active area partially isolated by a lateral cavity
A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the...
US-7,332,789 Isolation trenches for memory devices
Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper...
US-7,332,786 Anti-blooming storage pixel
Embodiments of the present invention provide pixel cells with increased storage capacity, which are capable of anti-blooming operations. In an exemplary...
US-7,332,773 Vertical device 4F.sup.2 EEPROM memory
EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate memory cells and select gates in NOR or NAND high density memory...
US-7,332,767 High density memory devices having improved channel widths and cell size
A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars...
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