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Patent # Description
US-7,339,839 Triggering of IO equilibrating ending signal with firing of column access signal
A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ...
US-7,339,838 Method and apparatus for supplementary command bus
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command...
US-7,339,830 One transistor SOI non-volatile random access memory cell
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried...
US-7,339,818 Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-7,339,812 Stacked 1T-nmemory cell structure
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell...
US-7,339,811 Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading...
US-7,339,431 CMOS amplifiers with frequency compensating capacitors
The frequency and transient responses of a CMOS differential amplifier are improved by employing one or more compensating capacitors. A compensating capacitor...
US-7,339,423 Technique to improve the gain and signal to noise ratio in CMOS switched capacitor amplifiers
The present invention comprises switched capacitor amplifiers including positive feedback on semiconductor devices, wafers, and systems incorporating same and...
US-7,339,408 Generating multi-phase clock signals using hierarchical delays
Circuits and methods for generating multi-phase clock signals using digitally-controlled hierarchical delay units (HDs) are provided. A plurality of...
US-7,339,239 Vertical NROM NAND flash memory array
Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM...
US-7,339,228 Non-planar flash memory array with shielded floating gates on silicon mesas
A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of...
US-7,339,217 High dynamic range image sensor
A pixel cell with controlled leakage is formed by modifying the location and gate profile of a high dynamic range (HDR) transistor. The HDR transistor may have a...
US-7,339,191 Capacitors having doped aluminum oxide dielectrics
Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation...
US-7,338,889 Method of improving copper interconnects of semiconductor devices for bonding
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,338,866 Strapping word lines of NAND memory devices
Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first...
US-7,338,856 Double-doped polysilicon floating gate
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes...
US-7,338,851 Diode/superionic conductor/polymer memory structure
A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second...
US-7,338,609 Partial edge bead removal to allow improved grounding during e-beam mask writing
A method to provide a ground point for second, or subsequent, e-beam mask-writing steps by selectively removing the photoresist edge bead of a photomask...
US-RE40,137 Methods for forming integrated circuits within substrates
.[.The invention includes methods for forming integrated circuits within substrates, and embedded circuits. In one aspect, the invention includes a method of...
US-7,337,404 Graphical representation of system information on a remote computer
A method and apparatus for gathering system information into a file and transmitting the file to a remote location for presentation as a graphical display. A...
US-7,337,088 Intelligent measurement modular semiconductor parametric test system
An intelligent measurement modular semiconductor parametric test system comprises an engine control module. The engine control module is operable to communicate...
US-7,336,548 Clock generating circuit with multiple modes of operation
A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding to the relative phases of an output clock...
US-7,336,547 Memory device having conditioning output data
A memory device has a memory array for storing memory data, a conditioning data storage unit for storing conditioning data, and data lines for transferring data....
US-7,336,541 NAND flash memory cell programming
A flash memory device, such as a NAND flash, is included having an array of floating gate transistor memory cells arranged in a first and second addressable...
US-7,336,537 Handling defective memory blocks of NAND memory devices
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the...
US-7,336,536 Handling defective memory blocks of NAND memory devices
Apparatus and methods are provided. A NAND memory device has a memory array comprising a plurality of memory blocks and a volatile latch coupled to each of the...
US-7,336,531 Multiple level cell memory device with single bit per cell, re-mappable memory block
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode...
US-7,336,522 Apparatus and method to reduce undesirable effects caused by a fault in a memory device
A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage...
US-7,336,430 Extended depth of field using a multi-focal length lens with a controlled range of spherical aberration and a...
An extended depth of field is achieved by a computational imaging system that combines a multifocal imaging subsystem for producing a purposefully blurred...
US-7,336,111 Fast-locking digital phase locked loop
An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization...
US-7,336,106 Phase detector and method having hysteresis characteristics
A phase detector generates a first output signal if a feedback clock signal leads a reference clock signal by more than a first time. The phase detector...
US-7,336,084 Delay lock circuit having self-calibrating loop
A delay lock circuit includes a measuring path, a forward path, and a feedback path. The measuring path samples a pulse with a reference signal in a measurement...
US-7,335,994 Semiconductor component having multiple stacked dice
A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for...
US-7,335,988 Use of palladium in IC manufacturing with conductive polymer bump
An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible...
US-7,335,985 Method and system for electrically coupling a chip to chip package
A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and...
US-7,335,981 Methods for creating electrophoretically insulated vias in semiconductive substrates
Methods are provided for creating lined vias in semiconductor substrates. Using electrophoretic deposition techniques, micelles of a lining material are...
US-7,335,978 Semiconductor component having stiffener, circuit decal and terminal contacts
A semiconductor component includes a stiffener, a circuit decal attached to the stiffener, and a semiconductor die attached to the stiffener. The circuit decal...
US-7,335,968 High permeability composite films to reduce noise in high speed interconnects
A transmission line circuit provides a structure for improved transmission line operation on integrated circuits. The transmission line circuit includes a first...
US-7,335,965 Packaging of electronic chips with air-bridge structures
A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly...
US-7,335,963 Light block for pixel arrays
Imager devices are formed with light block material between microlenses to enhance the characteristics of image acquisition. The light block material may be...
US-7,335,962 Photonic crystal-based lens elements for use in an image sensor
The invention, in various exemplary embodiments, incorporates a photonic crystal lens element into an image sensor. The photonic crystal lens element comprises a...
US-7,335,958 Tailoring gate work-function in image sensors
Embodiments of the invention provide a method of forming a pixel cell and the resultant pixel cell a photo-conversion device formed at a surface of a substrate...
US-7,335,935 Semiconductor structures
Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be...
US-7,335,571 Method of making a semiconductor device having an opening in a solder mask
A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior...
US-7,335,533 Methods for assembling semiconductor devices in superimposed relation with adhesive material defining the...
A method for assembling semiconductor devices includes providing a first semiconductor device, applying a predetermined volume of adhesive material to at least a...
US-7,335,525 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,335,396 Methods for controlling mass flow rates and pressures in passageways coupled to reaction chambers and systems...
Methods, apparatuses, and systems for controlling mass flow rates and pressures in passageways coupled to reaction chambers are disclosed herein. In one...
US-RE40,114 Tungsten silicide (WSIX) deposition process for semiconductor manufacture
A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the...
US-7,333,908 Techniques for generating test patterns in high speed memory devices
A system and methods for calibrating a memory device are provided. More specifically, a technique for internally generating a test pattern within a memory device...
US-7,333,674 Suppression of ringing artifacts during image resizing
An economical method of detecting and suppressing ringing artifacts during digital image resizing is presented. The economical method substitutes costly division...
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