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Patent # Description
US-7,332,767 High density memory devices having improved channel widths and cell size
A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars...
US-7,332,759 Method and structure to reduce optical crosstalk in a solid state imager
Methods and structures to reduce optical crosstalk in solid state imager arrays. Sections of pixel material layers that previously would have been etched away...
US-7,332,737 Isolation trench geometry for image sensors
A pixel cell including a substrate having a top surface. A photo-conversion device is at a surface of the substrate and a trench is in the substrate adjacent the...
US-7,332,735 Phase change memory cell and method of formation
A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase...
US-7,332,703 Imaging structure including a pixel with multiple signal readout circuits and methods of operation for imaging...
A pixel cell allows both correlated double sampling (CDS) and automatic light control (ALC) operations through a non-destructive, parallel readout. An image...
US-7,332,442 Systems and methods for forming metal oxide layers
A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or...
US-7,332,419 Structure and method of fabricating a transistor having a trench gate
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with...
US-7,332,418 High-density single transistor vertical memory gain cell
A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate....
US-7,332,413 Semiconductor wafers including one or more reinforcement structures and methods of forming the same
Methods of forming semiconductor devices include thinning a region of a semiconductor wafer and forming at least one semiconductor die laterally within a thinned...
US-7,332,408 Isolation trenches for memory devices
Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper...
US-7,332,401 Method of fabricating an electrode structure for use in an integrated circuit
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the...
US-7,332,389 Selective polysilicon stud growth
A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by...
US-7,332,388 Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates...
A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The...
US-7,332,376 Method of encapsulating packaged microelectronic devices with a barrier
Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the...
US-7,332,372 Methods for forming assemblies and packages that include stacked semiconductor devices separated a distance...
A method for assembling semiconductor devices includes providing a first semiconductor device, applying a volume of adhesive material to at least a surface of...
US-7,332,032 Precursor mixtures for use in preparing layers on substrates
Methods of forming a layer on a substrate using complexes of Formula I. The complexes and methods are particularly suitable for the preparation of semiconductor...
US-7,330,992 System and method for read synchronization of memory modules
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors,...
US-7,330,929 CAM modified to be used for statistic calculation in network switches and routers
A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the...
US-7,330,869 Hybrid arithmetic logic unit
Methods and apparatus for improving the efficiency of an arithmetic logic unit (ALU) are provided. The ALU of the invention combines the operation of a...
US-7,330,393 Memory array decoder
An apparatus and method for selecting a storage location in a memory device including receiving at least one of a pre-decoded location address signal, a match...
US-7,330,390 Noise resistant small signal sensing circuit for a memory device
Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus...
US-7,330,382 Programmable DQS preamble
A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where...
US-7,330,367 Stacked 1T-nMTJ MRAM structure
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ...
US-7,330,211 Camera module with focus adjustment structure and systems and methods of making the same
Camera modules with focus adjustment structures and systems and methods of making the same are described. In one aspect, a sensor housing having an image sensor,...
US-7,330,146 Minimized SAR-type column-wide ADC for image sensors
An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A...
US-7,330,036 Engagement Probes
An engagement probe for engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof...
US-7,329,949 Packaged microelectronic devices and methods for packaging microelectronic devices
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
US-7,329,945 Flip-chip adaptor package for bare die
A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or...
US-7,329,943 Microelectronic devices and methods for forming interconnects in microelectronic devices
Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In...
US-7,329,924 Integrated circuits and methods of forming a field effect transistor
Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate...
US-7,329,920 Trench corner effect bidirectional flash memory cell
A non-volatile memory cell structure that is capable of holding two data bits. The structure includes a trench in a substrate with two sides of the trench being...
US-7,329,917 Permeable capacitor electrode
The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors...
US-7,329,910 Semiconductor substrates and field effect transistor constructions
The invention includes methods of forming field effect transistor gates. In one implementation, a series of layers is formed proximate a semiconductive material...
US-7,329,899 Wafer-level redistribution circuit
A semiconductor component configured for wafer-level testing includes a semiconductor die having at least one die contact electrically exposed for coupling with...
US-7,329,861 Integrally packaged imaging module
An integrally packaged imaging module includes an integrated circuit (IC), including an image sensing device formed on a semiconductor substrate, and wafer level...
US-7,329,856 Image sensor having integrated infrared-filtering optical device and related method
An image sensing device is disclosed having a die formed with an array of photosensing sites and a structure of optical material having infrared absorbing...
US-7,329,618 Ion implanting methods
An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair...
US-7,329,615 Atomic layer deposition method of forming an oxide comprising layer on a substrate
This invention includes atomic layer deposition methods of depositing oxide comprising layers on substrates. In one implementation, a substrate is positioned...
US-7,329,607 Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby
A conductive connection forming method includes forming a first layer comprising a first metal on a substrate and forming a second layer comprising a second...
US-7,329,576 Double-sided container capacitors using a sacrificial layer
Double-sided container capacitors are formed using sacrificial layers. A sacrificial layer is formed within a recess in a structural layer. A lower electrode is...
US-7,329,573 Methods of forming capacitors
A method of forming a capacitor includes forming a first capacitor electrode over a semiconductor substrate. A capacitor dielectric region is formed onto the...
US-7,329,558 Differential negative resistance memory
The invention relates to a DNR (differential negative resistance) exhibiting device that can be programmed to store information as readable current amplitudes...
US-7,329,552 Field effect transistor fabrication methods, field emission device fabrication methods, and field emission...
The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors....
US-7,329,292 Process byproduct trap and system including same
A trap device including at least one substance delivery element for introducing a substance therein is disclosed. The delivered substance may influence the...
US-7,329,168 Extended Kalman filter incorporating offline metrology
An algorithm uses offline metrology to control a process by passing information from an outer control loop to an inner control loop, extended Kalman filter...
US-7,328,517 Method and apparatus for measurement of thickness and warpage of substrates
An apparatus comprises one or more pairs of mutually coaxial and opposing linear measuring devices including movable, biased fingers for simultaneously...
US-RE40,061 Multi-chip stacked devices
A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking...
US-7,328,425 Method and device for correcting SLM stamp image imperfections
The invention relates to production and precision patterning of work pieces, including manufacture of photomask for photolithography and direct writing on other...
US-7,328,381 Testing system and method for memory modules having a memory hub architecture
A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method...
US-7,328,379 Look-up table for use with redundant memory
A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is...
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