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Patent # Description
US-7,327,629 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,327,628 Circuit and method for reading an antifuse
An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing...
US-7,327,618 Semiconductor memory with wordline timing
A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section...
US-7,327,592 Self-identifying stacked die semiconductor components
A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a...
US-7,327,393 CMOS image sensor with variable conversion gain
An image sensor pixel has variable conversion gain to prevent overexposure of the pixel without reducing the exposure period. Under dim lighting conditions, the...
US-7,327,263 Communications system and method with A/D converter
A communications system includes a radio frequency identification device including an integrated circuit having a single die including a microprocessor, a...
US-7,327,173 Delay-locked loop having a pre-shift phase detector
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first...
US-7,327,034 Compositions for planarization of metal-containing surfaces using halogens and halide salts
A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a ...
US-7,327,016 High permeability composite films to reduce noise in high speed interconnects
An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation...
US-7,326,984 MIS capacitor and method of formation
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,326,980 Devices with HfSiON dielectric films which are Hf-O rich
A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an...
US-7,326,960 Semiconductor circuit constructions
The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor...
US-7,326,950 Memory device with switching glass layer
A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.
US-7,326,904 In-pixel kTC noise suppression using circuit techniques
A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within...
US-7,326,647 Dry etching process to form a conductive layer within an opening without use of a mask during the formation of...
A method for use in fabrication of a semiconductor device comprises forming a conformal conductive layer over a planarized surface of a dielectric layer, and...
US-7,326,611 DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The...
US-7,326,607 Imager floating diffusion region and process for forming same
The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a...
US-7,326,606 Semiconductor processing methods
In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to...
US-7,326,597 Gettering using voids formed by surface transformation
One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of...
US-7,326,591 Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods...
Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed...
US-7,326,503 Process for color filter array residual pigment removal
A method of fabricating a color filter array including the removal of unwanted residual color pigments. A substrate is coated with a colored photoresist layer....
US-7,326,316 Electrical interconnect using locally conductive adhesive
An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one...
US-7,326,105 Retaining rings, and associated planarizing apparatuses, and related methods for planarizing micro-device...
Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head...
US-7,326,066 Adapter for non-permanently connecting integrated circuit devices to multi-chip modules and method of using same
An adapter and method for aligning and connecting the external leads of at least one integrated circuit device to conductors on a substrate of a multi-chip...
US-7,325,089 Controller for refreshing memories
A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device...
US-7,324,690 Metal mask for light intensity determination and ADC calibration
An apparatus and method for controlling gain characteristics in a CMOS imager and for calibrating light intensity and analog to digital conversion in a pixel...
US-7,324,401 Memory device and method having programmable address configurations
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of...
US-7,324,400 Programming and evaluating through PMOS injection
A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The...
US-7,324,383 Selective slow programming convergence in a flash memory device
A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After...
US-7,324,381 Low power multiple bit sense amplifier
A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers...
US-7,324,367 Memory cell and method for forming the same
A semiconductor memory cell structure having 4 F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and...
US-7,324,290 Variable focus optic module and optic system
A variable focus optic module is provided with a housing, a lens assembly, and a protrusion and recess system. The lens assembly is movably disposed in operable...
US-7,323,896 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer
A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are...
US-7,323,772 Ball grid array structures and tape-based method of manufacturing same
Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using...
US-7,323,767 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,323,756 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,323,755 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,323,739 Semiconductor device having recess and planarized layers
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a...
US-7,323,738 MIS capacitor and method of formation
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,323,737 DRAM constructions and electronic systems
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal...
US-7,323,424 Semiconductor constructions comprising cerium oxide and titanium oxide
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can...
US-7,323,412 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times...
US-7,323,400 Plasma processing, deposition and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...
US-7,323,380 Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
US-7,323,353 Resonator for thermo optic device
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is...
US-7,323,292 Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures...
A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of...
US-7,323,291 Dual layer workpiece masking and manufacturing process
The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described...
US-7,323,231 Apparatus and methods for plasma vapor deposition processes
One aspect of the invention is directed toward a method of forming a conductive layer on a microfeature workpiece. In one embodiment, the method comprises...
US-7,323,064 Supercritical fluid technology for cleaning processing chambers and systems
The invention includes a method of cleaning a processing chamber by introducing supercritical fluid into the processing chamber. A residue over an internal...
US-7,322,511 Apparatus and method for printing micro metal structures
A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using...
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