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| Patent # | Description |
|---|---|
| US-7,482,176 |
Etch mask and method of forming a magnetic random access memory structure A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering... |
| US-7,482,037 |
Methods for forming niobium and/or vanadium containing layers using atomic
layer deposition A method of forming a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a... |
| US-7,481,887 |
Apparatus for controlling gas pulsing in processes for depositing
materials onto micro-device workpieces An apparatus for depositing materials onto a micro-device workpiece includes a gas source system configured to provide a first precursor, a second precursor, and... |
| US-7,480,792 |
Memory modules having accurate operating parameters stored thereon and
methods for fabricating and implementing... Memory modules having accurate operating parameters stored thereon and methods for fabricating and implementing such devices to improve system performance.... |
| US-7,480,762 |
Erase block data splitting A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data... |
| US-7,480,203 |
Method and apparatus for initialization of read latency tracking circuit
in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a... |
| US-7,480,202 |
High speed array pipeline architecture A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into... |
| US-7,480,199 |
Method for low power refresh of a dynamic random access memory using a
slower refresh rate than a normal... A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data... |
| US-7,480,195 |
Internal data comparison for memory testing Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data... |
| US-7,480,186 |
NROM flash memory with self-aligned structural charge separation A nitride read only memory (NROM) cell has a nitride layer that is not located under the center of the transistor. The gate insulator layer, with the nitride... |
| US-7,480,185 |
Ballistic injection NROM flash memory A split NROM flash memory cell is comprised of source/drain regions in a substrate. The split nitride charge storage regions are insulated from the substrate by... |
| US-7,480,098 |
Microlens array sheet having black matrix and method of manufacturing the
same Disclosed herein are a microlens array sheet having a black matrix and a method for manufacturing the same. The manufacturing method includes a) the step of... |
| US-7,479,650 |
Method of manufacture of programmable conductor memory Programmable conductor memory cells in a stud configuration are fabricated in an integrated circuit by blanket deposition of layers. The layers include a bottom... |
| US-7,479,440 |
Method of forming an isolation structure that includes forming a silicon
layer at a base of the recess A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a... |
| US-7,479,413 |
Method for fabricating semiconductor package with circuit side polymer
layer A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a... |
| US-7,479,206 |
Apparatus for in-situ optical endpointing on web-format planarizing
machines in mechanical or... Polishing pads, planarizing machines and methods for mechanical and/or chemical-mechanical planarization of microelectronic-device substrate assemblies. The... |
| US-RE40,623 |
Method and apparatus for identifying integrated circuits An integrated circuit and method for identifying same is described. The integrated circuit includes a programmable identification circuit for storing electronic... |
| US-7,478,032 |
Method and system for selecting compatible processors to add to a
multiprocessor computer A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program... |
| US-7,477,570 |
Sequential access memory with system and method A sequential access memory ("SAM") device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality... |
| US-7,477,557 |
256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array... |
| US-7,477,556 |
256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array... |
| US-7,477,554 |
Data retention kill function A method for operating a memory device is disclosed. In one embodiment, the method includes receiving authorized operating parameters of the memory device and... |
| US-7,477,542 |
Split gate flash memory cell with ballistic injection A split floating gate flash memory cell includes source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of... |
| US-7,477,306 |
Method and apparatus for improving pixel output swing in imager sensors A bias readout circuit is disclosed for use in reading out a pixel of an imager system. The bias readout circuit includes a circuit portion which mirrors an... |
| US-7,477,304 |
Two narrow band and one wide band color filter for increasing color image
sensor sensitivity A color filter to increase the low light sensitivity of an image sensor. The color filter has two narrow band color filters and one wide band filter. Also... |
| US-7,477,298 |
Anti-eclipsing circuit for image sensors An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection... |
| US-7,476,955 |
Die package having an adhesive flow restriction area A die package having an adhesive flow restriction area. In a first embodiment, the adhesive flow restriction area is formed as a trench in a transparent element.... |
| US-7,476,933 |
Vertical gated access transistor According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow... |
| US-7,476,927 |
Scalable multi-functional and multi-level nano-crystal non-volatile memory
device A multi-functional and multi-level memory cell is comprised of a tunnel layer formed over a substrate. In one embodiment, the tunnel layer is comprised of two... |
| US-7,476,925 |
Atomic layer deposition of metal oxide and/or low asymmetrical tunnel
barrier interploy insulators Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The... |
| US-7,476,861 |
Passenger detection apparatus A passenger detection device that determines whether a passenger sits in a passenger seat or backseat, and if YES, determines whether the passenger is an adult... |
| US-7,476,836 |
Multi-point correlated sampling for image sensors An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating... |
| US-7,476,588 |
Methods of forming NAND cell units with string gates of various widths Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string... |
| US-7,476,586 |
NOR flash memory cell with high storage density Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor... |
| US-7,476,556 |
Systems and methods for plasma processing of microfeature workpieces Systems and methods for plasma processing of microfeature workpieces are disclosed herein. In one embodiment, a method includes generating a plasma in a chamber... |
| US-7,476,305 |
Recovery system for platinum plating bath A recovery system for platinum electrolytic baths operating at low current densities is disclosed. An oxidizing system is provided in a closed-loop recirculation... |
| US-7,476,277 |
Apparatus for improving stencil/screen print quality A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a... |
| US-7,475,137 |
Methods of operating portable computerized device with network security A multi-level network security system is disclosed for a computer host device coupled to at least one computer network. The system including a secure network... |
| US-7,474,846 |
Method and apparatus of determining the best focus position of a lens A method and apparatus for accurately auto focusing a lens of an imaging device. An imaged scene is split into an array of zones. The minimum and maximum... |
| US-7,474,560 |
Non-volatile memory with both single and multiple level cells Memory arrays, and modules, devices and systems that utilize such memory arrays, are described as having a single level non-volatile memory cell interposed... |
| US-7,474,111 |
Electrical probe assembly with guard members for the probes The probe assembly has a plurality of probes, a probe base provided with the probes, and a plurality of guard members provided on the probe base. Each probe has... |
| US-7,473,956 |
Atomic layer deposition of metal oxide and/or low assymmetrical tunnel
barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The... |
| US-7,473,662 |
Metal-doped alumina and layers thereof A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate... |
| US-7,473,645 |
Method of depositing a layer comprising silicon, carbon, and fluorine onto
a semiconductor substrate The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and... |
| US-7,473,644 |
Method for forming controlled geometry hardmasks including subresolution
elements Methods for forming accurate, symmetric cross-section spacers of hardmask material on a substrate such as a silicon wafer or quartz substrate, for formation of... |
| US-7,473,637 |
ALD formed titanium nitride films The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices.... |
| US-7,473,615 |
Semiconductor processing methods The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can... |
| US-7,473,613 |
Terraced film stack A process directed to forming a terraced film stack of a semiconductor device, for example, a DRAM memory device, is disclosed. The present invention addresses... |
| US-7,473,596 |
Methods of forming memory cells An integrated circuit memory cell includes a combined first capacitor electrode and first transistor source/drain, a second capacitor electrode, a capacitor... |
| US-7,473,582 |
Method for fabricating semiconductor component with thinned substrate
having pin contacts A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor... |
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