Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: micron





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,358,139 Method of forming a field effect transistor including depositing and removing insulative material effective to...
The invention includes methods of forming field effect transistors. In one implementation, a method of forming a field effect transistor having a gate comprising...
US-7,358,131 Methods of forming SRAM constructions
The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge....
US-7,358,117 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
US-7,358,103 Method of fabricating an imaging device for collecting photons
A photon collector has a reflecting metal layer to increase photon collection efficiency in a solid state imaging sensor. The reflecting metal layer reflects...
US-7,357,695 Systems and methods for mechanical and/or chemical-mechanical polishing of microfeature workpieces
Systems and methods for polishing microfeature workpieces. In one embodiment, a method includes determining a status of a characteristic of a microfeature...
US-D566,709 Storage device
US-7,356,723 Method and apparatus for data transfer
A memory system and method according to various aspects of the present invention comprises a memory and an adaptive timing system for controlling access to the...
US-7,355,922 Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM
A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a...
US-7,355,920 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,355,894 Programming flash memories
A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control...
US-7,355,464 Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency
A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows...
US-7,355,423 Method for optimizing probe card design
A method is presented of designing semiconductor probe cards to have the optimum number and placement of die probe sites for function testing integrated circuit...
US-7,355,387 System and method for testing integrated circuit timing margins
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,355,273 Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods
An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and...
US-7,355,267 Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of...
A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed...
US-7,355,244 Electrical devices with multi-walled recesses
The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate...
US-7,355,232 Memory devices with dual-sided capacitors
A dual-sided HSG capacitor and a method of fabrication are disclosed. A thin native oxide layer is formed between a doped polycrystalline layer and a layer of...
US-7,355,231 Memory circuitry with oxygen diffusion barrier layer received over a well base
A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured...
US-7,355,229 Masked spacer etching for imagers
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel...
US-7,355,222 Imaging device having a pixel cell with a transparent conductive interconnect line and the method of making the...
The invention relates to an imaging device having a pixel cell with a transparent conductive material interconnect line for focusing incident light onto a...
US-7,355,203 Use of gate electrode workfunction to improve DRAM refresh
This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes,...
US-7,354,863 Methods of selectively removing silicon
An etch solution that comprises tetramethylammonium hydroxide ("TMAH") and at least one organic solvent. The etch solution may be substantially free of water....
US-7,354,842 Methods of forming conductive materials
The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic...
US-7,354,812 Multiple-depth STI trenches in integrated circuit fabrication
Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation...
US-7,354,795 Methods for packaging and encapsulating semiconductor device assemblies that include tape substrates
Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a...
US-7,354,793 Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element
A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and...
US-7,354,631 Chemical vapor deposition apparatus and methods
This invention includes chemical vapor deposition apparatus, methods of chemical vapor depositing an amorphous carbon comprising layer on a substrate, and...
US-7,354,329 Method of forming a monolithic base plate for a field emission display (FED) device
A substrate is provided and is configurable into a base plate for a field emission display. A plurality of discrete, segmented regions of field emitter tips are...
US-7,353,437 System and method for testing a memory for a memory failure exhibited by a failing memory
A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a...
US-7,353,320 Memory hub and method for memory sequencing
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system...
US-7,353,316 System and method for re-routing signals between memory system components
A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are...
US-7,353,281 Method and system for providing access to computer resources
A method and computer system for providing access to computer resources on a computer system and includes generating a token containing encrypted user...
US-7,352,892 System and method for shape reconstruction from optical images
Reconstructing the shape of the surface of an object in greater than two dimensions is performed using a noise-tolerant reconstruction process and/or a...
US-7,352,649 High speed array pipeline architecture
A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into...
US-7,352,643 Regulating voltages for refresh operation using flash trim bits in semiconductor memory devices
A method and apparatus for regulating voltages in semiconductor devices. Trim bits are stored in a trim flash array, where the trim bits define a voltage value...
US-7,352,624 Reduction of adjacent floating gate data pattern sensitivity
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate...
US-7,352,603 Apparatus and methods for optically-coupled memory systems
Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier...
US-7,352,602 Configurable inputs and outputs for memory stacking system and method
Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of...
US-7,352,511 Micro-lenses for imagers
A micro-lens and a method for forming the micro-lens is provided. A micro-lens includes a substrate and lens material located within the substrate, the substrate...
US-7,352,201 System and method for testing devices utilizing capacitively coupled signaling
An apparatus and method for testing a semiconductor device in an AC test regime. The test apparatus includes a test plate capacitively couple to the signal...
US-7,352,023 Constructions comprising hafnium oxide
The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is...
US-7,352,019 Capacitance reduction by tunnel formation for use with a semiconductor device
A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the...
US-7,352,007 Phosphorescent nanotube memory device
An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material...
US-7,351,945 Alignment among elements in an image sensor
An image sensor is formed with shifts among the optical parts of the sensor and the photosensitive parts of the sensor. The optical parts of the sensor may...
US-7,351,659 Methods of forming a transistor with an integrated metal silicide gate electrode
Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is...
US-7,351,640 Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules
Methods are provided for robust and cost effective techniques to fabricate a semiconductor device having double-sided hemispherical silicon grain (HSG)...
US-7,351,628 Atomic layer deposition of CMOS gates with variable work functions
Structures, systems and methods for transistors having gates with variable work functions formed by atomic layer deposition are provided. One transistor...
US-7,351,620 Methods of forming semiconductor constructions
The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional...
US-7,350,182 Methods of forming patterned reticles
The invention includes methods of forming patterned reticles. Design features can be introduced into a layout for a reticle prior to optical proximity...
US-7,350,093 Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.