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Memory device interface
An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based...
Automatic color constancy for image sensors
An electronic imaging system operates as closely as possible to the cone spectral response space to obtain a human eye-like long, medium, short (LMS) wavelength...
Low supply voltage temperature compensated reference voltage generator and
A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage....
Method and system for monitoring plasma using optical emission
A method and system are presented for monitoring the optical emissions associated with a plasma used in integrated circuit fabrication. The optical emissions may...
CMOS circuits with reduced crowbar current
Various circuit embodiments comprise an input node to receive an input signal for a CMOS transistor stack, a first output node to deliver the input signal to a...
Chip scale package with heat spreader
A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame...
Lanthanide oxide / hafnium oxide dielectric layers
Dielectric layers containing a hafnium oxide hafnium oxide layer arranged as one or more monolayers and a lanthanide oxide layer and a method of fabricating such...
CMOS imaging for ALC and CDS
Embodiments of the invention provide pixel cells that allow both automatic light control and correlated double sampling operations. The pixel cell includes first...
Selective passivation of exposed silicon
A method for applying a passivation layer selectively on an exposed silicon surface includes use of a liquid phase solution supersaturated in silicon dioxide....
Atomic layer deposition methods, and methods of forming materials over
The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times...
Compositions for dissolution of low-k dielectric films, and methods of use
An improved composition and method for cleaning the surface of a semiconductor wafer are provided. The composition can be used to selectively remove a low-k...
Method for obtaining extreme selectivity of metal nitrides and metal
Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the...
Packaged microelectronic devices and methods for packaging microelectronic
Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a ...
Laser assisted material deposition
A method of forming a film on a substrate includes activating a gas precursor to form a material on the substrate by irradiating the gas precursor with...
Method for binding halide-based contaminants during formation of a
A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized...
System and method for on-board timing margin testing of memory modules
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors,...
Memory hub tester interface and method for use thereof
A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a...
Memory device and method having data path with multiple prefetch I/O
A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into...
Access circuit and method for allowing external test voltage to be applied
to isolated wells
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are...
Local digit line architecture and method for memory devices having
multi-bit or low capacitance memory cells
A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively...
Closed-loop high voltage booster
A voltage boosting circuit with a closed-loop control mechanism and a controllable slew rate. A tracking capacitor and a control current form the closed-loop and...
Method and apparatus providing input buffer design using common-mode
An input buffer includes a first stage for receiving an input signal and having a first pair of complementary output signals, the first stage including an input...
Method, apparatus, and system for low voltage temperature sensing
A temperature sensor device and method of sensing temperature are disclosed. The device and method include generating a reference voltage inversely correlated to...
Constructions comprising perovskite-type dielectric
The invention includes a capacitor construction. A capacitor electrode has a perovskite-type dielectric material thereover. The perovskite-type dielectric...
Method of fabricating a stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
Method for quartz bump defect repair with less substrate damage
A method for minimizing damage to a substrate while repairing a defect in a phase shifting mask for an integrated circuit comprising locating a bump defect in a...
Apparatus and method for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output...
Software refreshed memory device and method
A software refreshed memory device comprises a plurality of memory cells that must be periodically refreshed to avoid losing data. Preferably, the memory cells...
Apparatus and method for improving dynamic refresh in a memory device
An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time...
Detection of row-to-row shorts and other row decode defects in memory
A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage...
Static content addressable memory cell
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second...
Soldermask opening to prevent delamination
A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are...
Gapless microlens array and method of fabrication
A microlens array having first and second sets of spherically-shaped microlenses. The second set of spherically-shaped microlenses are located in the areas...
Technique for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over...
Semiconductor components having through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact....
Reduced crosstalk CMOS image sensors
CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A...
Etch mask and method of forming a magnetic random access memory structure
A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering...
Stepped gate configuration for non-volatile memory
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric...
Microelectronic devices and methods for manufacturing and operating
packaged microelectronic device assemblies
Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged...
Process flow for building MRAM structures
MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching...
In-situ chemical-mechanical planarization pad metrology using ultrasonic
Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe...
Command sequence for optimized power consumption
Power consumption by a memory device may be controlled by maintaining data input buffers in an off state until a command sequence containing a specified command...
Computer touch screen adapted to facilitate selection of features at edge
In one embodiment of the invention, a hot spot is normally centered in an area of contact between a user's finger and a touch screen to position the hot spot on...
Method and apparatus for digital phase generation for high frequency clock
An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal....
Interconnect for testing semiconductor components
An interconnect for testing semiconductor components includes interconnect contacts configured for bonding to, and then separation from component contacts on the...
Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
Chalcogenide-based electrokinetic memory element and method of forming the
Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a...
Formation of standard voltage threshold and low voltage threshold MOSFET
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
Atomic layer deposition methods
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a...