Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching: micron
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| US-7,326,611 |
DRAM arrays, vertical transistor structures and methods of forming
transistor structures and DRAM arrays The invention includes a method of forming a semiconductor construction. Dopant is implanted into the upper surface of a monocrystalline silicon substrate. The... |
| US-7,326,607 |
Imager floating diffusion region and process for forming same The present invention provides an imager device with a floating diffusion region resistant to charge leakage. The floating diffusion region is formed having a... |
| US-7,326,606 |
Semiconductor processing methods In one aspect, the invention provides a method of forming a contact opening to a conductive line. In one preferred implementation, a contact opening is formed to... |
| US-7,326,597 |
Gettering using voids formed by surface transformation One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of... |
| US-7,326,591 |
Interconnecting substrates for microelectronic dies, methods for forming
vias in such substrates, and methods... Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed... |
| US-7,326,503 |
Process for color filter array residual pigment removal A method of fabricating a color filter array including the removal of unwanted residual color pigments. A substrate is coated with a colored photoresist layer.... |
| US-7,326,316 |
Electrical interconnect using locally conductive adhesive An anisotropic electrically conducting interconnect is disclosed in which an adhesive comprising particles having a breakable coating of at feast one... |
| US-7,326,105 |
Retaining rings, and associated planarizing apparatuses, and related
methods for planarizing micro-device... Retaining rings and associated planarizing apparatuses, and related methods for planarizing micro-device workpieces are disclosed herein. A carrier head... |
| US-7,326,066 |
Adapter for non-permanently connecting integrated circuit devices to
multi-chip modules and method of using same An adapter and method for aligning and connecting the external leads of at least one integrated circuit device to conductors on a substrate of a multi-chip... |
| US-7,325,089 |
Controller for refreshing memories A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device... |
| US-7,324,690 |
Metal mask for light intensity determination and ADC calibration An apparatus and method for controlling gain characteristics in a CMOS imager and for calibrating light intensity and analog to digital conversion in a pixel... |
| US-7,324,401 |
Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of... |
| US-7,324,400 |
Programming and evaluating through PMOS injection A PMOS transistor includes a gate, drain, and source in a substrate and is isolated from adjacent transistors in the substrate by shallow trench isolation. The... |
| US-7,324,383 |
Selective slow programming convergence in a flash memory device A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After... |
| US-7,324,381 |
Low power multiple bit sense amplifier A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers... |
| US-7,324,367 |
Memory cell and method for forming the same A semiconductor memory cell structure having 4 F.sup.2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and... |
| US-7,324,290 |
Variable focus optic module and optic system A variable focus optic module is provided with a housing, a lens assembly, and a protrusion and recess system. The lens assembly is movably disposed in operable... |
| US-7,323,896 |
Device and method for isolating a short-circuited integrated circuit (IC)
from other ICs on a semiconductor wafer A circuit for isolating a short-circuited integrated circuit (IC) formed on the surface of a semiconductor wafer from other ICs formed on the wafer that are... |
| US-7,323,772 |
Ball grid array structures and tape-based method of manufacturing same Semiconductor device packages formed in accordance with methods of packaging semiconductor dice in grid array-type semiconductor device packages using... |
| US-7,323,767 |
Standoffs for centralizing internals in packaging process A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the... |
| US-7,323,756 |
Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes... |
| US-7,323,755 |
Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes... |
| US-7,323,739 |
Semiconductor device having recess and planarized layers A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a... |
| US-7,323,738 |
MIS capacitor and method of formation An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to... |
| US-7,323,737 |
DRAM constructions and electronic systems The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal... |
| US-7,323,424 |
Semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can... |
| US-7,323,412 |
Atomic layer deposition methods, and methods of forming materials over
semiconductor substrates The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times... |
| US-7,323,400 |
Plasma processing, deposition and ALD methods A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing... |
| US-7,323,380 |
Single transistor vertical memory gain cell A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain... |
| US-7,323,353 |
Resonator for thermo optic device A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is... |
| US-7,323,292 |
Process for using photo-definable layers in the manufacture of
semiconductor devices and resulting structures... A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of... |
| US-7,323,291 |
Dual layer workpiece masking and manufacturing process The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described... |
| US-7,323,231 |
Apparatus and methods for plasma vapor deposition processes One aspect of the invention is directed toward a method of forming a conductive layer on a microfeature workpiece. In one embodiment, the method comprises... |
| US-7,323,064 |
Supercritical fluid technology for cleaning processing chambers and
systems The invention includes a method of cleaning a processing chamber by introducing supercritical fluid into the processing chamber. A residue over an internal... |
| US-7,322,511 |
Apparatus and method for printing micro metal structures A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using... |
| US-7,322,002 |
Erasure pointer error correction Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in... |
| US-7,321,951 |
Method for testing flash memory power loss recovery Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or... |
| US-7,321,504 |
Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter... |
| US-7,321,455 |
Microelectronic devices and methods for packaging microelectronic devices Microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, a method includes placing a plurality of... |
| US-7,321,160 |
Multi-part lead frame A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed... |
| US-7,321,150 |
Semiconductor device precursor structures to a double-sided capacitor or a
contact A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is... |
| US-7,321,149 |
Capacitor structures, and DRAM arrays A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer.... |
| US-7,321,148 |
Capacitor constructions and rugged silicon-containing surfaces The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at... |
| US-7,320,933 |
Double bumping of flexible substrate for first and second level
interconnects An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with... |
| US-7,320,911 |
Methods of forming pluralities of capacitors A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes... |
| US-7,320,049 |
Detection circuit for mixed asynchronous and synchronous memory operation A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit... |
| US-7,319,935 |
System and method for analyzing electrical failure data A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having... |
| US-7,319,728 |
Delay locked loop with frequency control A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the... |
| US-7,319,629 |
Method of operating a dynamic random access memory cell A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory... |
| US-7,319,621 |
Reducing DQ pin capacitance in a memory device A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.