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| Patent # | Description |
|---|---|
| US-7,388,391 |
Method for evaluating at least one electrical conducting structure of an
electronic component An apparatus and method for evaluating the integrity of each contact pin of an electronic component having multiple contact pins. In one embodiment, the... |
| US-7,388,294 |
Semiconductor components having stacked dice A semiconductor package component includes a base die and a secondary die flip chip mounted to the base die. The base die includes a set of stacking contacts for... |
| US-7,388,290 |
Spacer patterned, high dielectric constant capacitor and methods for
fabricating the same A high dielectric constant memory cell capacitor and method for producing the same, wherein the memory cell capacitor utilizes relatively large surface area... |
| US-7,388,289 |
Local multilayered metallization An interconnect comprises a trench and a number of metal layers above the trench. The trench has a depth and a width. The depth is greater than a critical depth,... |
| US-7,388,251 |
Non-planar flash memory array with shielded floating gates on silicon
mesas A first plane of memory cells is formed on mesas of the array. A second plane of memory cells is formed in valleys adjacent to the mesas. The second plurality of... |
| US-7,388,248 |
Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site... |
| US-7,388,246 |
Lanthanide doped TiO.sub.x dielectric films A dielectric film containing lanthanide doped TiO.sub.x and a method of fabricating such a dielectric film produce a reliable dielectric layer having an... |
| US-7,388,241 |
Pinned photodiode structure and method of formation An imager having a photodiode with a shallow doping profile with respect to the top surface of a substrate is disclosed. An imager with a graded pinned surface... |
| US-7,388,239 |
Frame shutter pixel with an isolated storage node A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent... |
| US-7,388,183 |
Low dark current pixel with a guard drive active photodiode A method and apparatus for reducing thermally generated dark current in a CMOS imaging device is disclosed. A photodiode within the imaging device is kept... |
| US-7,387,959 |
Method of fabricating integrated circuitry The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed... |
| US-7,387,940 |
Methods of forming trench isolation in the fabrication of integrated
circuitry, methods of fabricating memory... The invention includes methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating integrated circuitry including... |
| US-7,387,939 |
Methods of forming semiconductor structures and capacitor devices The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the... |
| US-7,387,912 |
Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly... |
| US-7,387,909 |
Methods of forming assemblies displaying differential negative resistance The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at... |
| US-7,387,908 |
CMOS imager with enhanced transfer of charge and low voltage operation and
method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region... |
| US-7,387,902 |
Methods for packaging image sensitive electronic devices The invention provides methods for packaging for electronic devices that are light or other radiation-sensitive, such as image sensors including CCD or CMOS... |
| US-7,387,866 |
Photolithography process using multiple anti-reflective coatings A method for fabricating an integrated circuit using a photo-lithographic process includes the steps of placing at least two anti-reflective coating layers... |
| US-7,387,853 |
Use of a planarizing layer to improve multilayer performance in
ultraviolet masks The present invention relates to fabricating a reticle or mask for use in an extreme ultraviolet ("EUV") photolithographic process. The EUV reticle comprises a... |
| US-7,387,685 |
Apparatus and method for depositing materials onto microelectronic
workpieces Reactors for vapor deposition of materials onto a microelectronic workpiece, systems that include such reactors, and methods for depositing materials onto... |
| US-7,387,119 |
Dicing saw with variable indexing capability A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be... |
| US-7,386,689 |
Method and apparatus for connecting a massively parallel processor array
to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be... |
| US-7,386,660 |
CAM with automatic writing to the next free address A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid... |
| US-7,386,657 |
Random access interface in a serial memory device A random access interface is provided to a non-volatile, serial memory array. An address multiplexer has an external address connection and a serial address... |
| US-7,386,649 |
Multiple processor system and method including multiple memory hub modules A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly... |
| US-7,386,186 |
Apparatus and method for processing images A method and apparatus for processing an image. Specifically, one exemplary embodiment of the method comprises inputting an image into a pixel array producing... |
| US-7,385,871 |
Apparatus for memory device wordline A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a... |
| US-7,385,868 |
Method of refreshing a PCRAM memory device A method for refreshing PCRAM cells programmed to a low resistance state and entire arrays of PCRAM cells uses a simple refresh scheme which does not require... |
| US-7,385,846 |
Reduction of adjacent floating gate data pattern sensitivity The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate... |
| US-7,385,842 |
Magnetic memory having synthetic antiferromagnetic pinned layer A magnetic memory element includes a sense structure, a tunnel barrier adjacent the sense structure, and a synthetic antiferromagnet (SAF) adjacent the tunnel... |
| US-7,385,547 |
Minimized differential SAR-type column-wide ADC for CMOS image sensors An analog-to-digital converter comprising a minimal amount of circuitry for conversion of an input analog signal to a series of digital bits. A differential... |
| US-7,385,412 |
Systems and methods for testing microfeature devices Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a... |
| US-7,385,298 |
Reduced-dimension microelectronic component assemblies with wire bonds and
methods of making same The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one... |
| US-7,385,290 |
Electrochemical reaction cell for a combined barrier layer and seed layer Methods and apparatus for forming conductive interconnect layers useful in articles such as semiconductor chips, memory devices, semiconductor dies, circuit... |
| US-7,385,259 |
Method of manufacturing a multilayered doped conductor for a contact in an
integrated circuit device A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method... |
| US-7,385,245 |
Low power memory subsystem with progressive non-volatility The memory system is comprised of a plurality of memory arrays that are coupled to a processor. The memory arrays are comprised of non-volatile memory cells that... |
| US-7,385,240 |
Storage cell capacitor compatible with high dielectric constant materials An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed... |
| US-7,385,238 |
Low dark current image sensors with epitaxial SiC and/or carbonated
channels for array transistors A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or... |
| US-7,385,232 |
CMOS imager with enhanced transfer of charge and low voltage operation and
method of formation A dopant gradient region of a first conductivity type and a corresponding channel impurity gradient below a transfer gate and adjacent a charge collection region... |
| US-7,385,222 |
Thin film transistors and semiconductor constructions A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a... |
| US-7,385,167 |
CMOS front end process compatible low stress light shield An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding... |
| US-7,385,166 |
In-pixel kTC noise suppression using circuit techniques A circuit and method for reducing kTC noise in CMOS imagers while minimizing power dissipation is disclosed. Correlated double sampling (CDS) is performed within... |
| US-7,384,849 |
Methods of forming recessed access devices associated with semiconductor
constructions The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the... |
| US-7,384,847 |
Methods of forming DRAM arrays The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array... |
| US-7,384,840 |
Bulk-isolated PN diode and method of forming a bulk-isolated PN diode A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another... |
| US-7,384,805 |
Transfer mold semiconductor packaging processes In one implementation, a circuit substrate includes a substrate having opposing sides. At least one of the sides is configured for transfer mold packaging and... |
| US-7,384,727 |
Semiconductor processing patterning methods The invention includes semiconductor processing patterning methods and semiconductor constructions. A semiconductor processing patterning method includes forming... |
| US-7,383,376 |
Apparatus and methods for storing data in a magnetic random access memory
(MRAM) An apparatus and methods store data in a magnetic random access memory (MRAM) in a fast and efficient manner. Embodiments advantageously decrease the number of... |
| US-7,383,182 |
Systems and methods for speech recognition and separate dialect
identification A speech-to-text conversion system. The two-way speech recognition and dialect system comprises a computer system, an attached microphone assembly, and... |
| US-7,383,147 |
Dynamically adaptable semiconductor parametric testing An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time... |
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