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| Patent # | Description |
|---|---|
| US-7,446,277 |
Method for sorting integrated circuit devices A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including... |
| US-7,446,028 |
Multi-component integrated circuit contacts An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a... |
| US-7,445,996 |
Low resistance peripheral contacts while maintaining DRAM array integrity A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device,... |
| US-7,445,991 |
Methods of forming a plurality of capacitors The invention includes methods of forming a plurality of capacitors. In one implementation, a plurality of capacitor electrode openings is formed over a... |
| US-7,445,990 |
Methods of forming a plurality of capacitors A plurality of capacitor electrode openings is formed within capacitor electrode-forming material. A first set of the openings is formed to a depth which is... |
| US-7,445,973 |
Transistor surround gate structure with silicon-on-insulator isolation for
memory cells, memory arrays, memory... A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed... |
| US-7,445,951 |
Trench photosensor for a CMOS imager A trench photosensor for use in a CMOS imager having an improved charge capacity. The trench photosensor may be either a photogate or photodiode structure. The... |
| US-7,444,934 |
Supercritical fluid-assisted direct write for printing integrated circuits High resolution patterns provided on a surface of a semiconductor substrate and methods of direct printing of such high resolution patterns are disclosed. The... |
| US-7,444,616 |
Method for error reduction in lithography The present invention relates to a method and a system for predicting and/or measuring and correcting geometrical errors in lithography using masks, such as... |
| US-7,444,579 |
Non-systematic coded error correction Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by encoding... |
| US-7,444,559 |
Generation of memory test patterns for DLL calibration A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through... |
| US-7,444,550 |
System and method for communicating a software-generated pulse waveform
between two servers in a network A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between... |
| US-7,444,537 |
System and method for communicating a software-generated pulse waveform
between two servers in a network A method of monitoring a status condition of a first server with a second server in a server network, and also providing synchronization and messaging between... |
| US-7,444,458 |
Method for assigning addresses to memory devices A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an... |
| US-7,444,030 |
Image encoding with dynamic buffer-capacity-level-based compression
adjustment Methods, systems, and computer programs for encoding images are described. In one aspect, quantized frequency domain vectors are sequentially generated from a... |
| US-7,443,761 |
Loop filtering for fast PLL locking Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL)... |
| US-7,443,750 |
Switched capacitor DRAM sense amplifier with immunity to mismatch and
offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor... |
| US-7,443,749 |
Switched capacitor DRAM sense amplifier with immunity to mismatch and
offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor... |
| US-7,443,743 |
Method and system for improved efficiency of synchronous mirror delays and
delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and... |
| US-7,443,715 |
SRAM cells with repressed floating gate memory, low tunnel barrier
interpoly insulators Structures and methods are provided for SRAM cells having a novel, non-volatile floating gate transistor, e.g. a non-volatile memory component, within the cell... |
| US-7,443,437 |
Image sensor with a gated storage node linked to transfer gate A CMOS imaging system with increased charge storage of pixels yet decreased physical size, kTC noise and active area. A storage node is connected to the transfer... |
| US-7,443,427 |
Wide dynamic range linear-and-log active pixel A pixel circuit having an improved dynamic range is disclosed. When incoming light detected by the photodiode is strong, the accumulated (integrated) charge on a... |
| US-7,443,219 |
Phase interpolation apparatus, systems, and methods A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal... |
| US-7,443,216 |
Trimmable delay locked loop circuitry with improved initialization
characteristics Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay... |
| US-7,443,038 |
Flip-chip image sensor packages The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the... |
| US-7,443,032 |
Memory device with chemical vapor deposition of titanium for titanium
silicide contacts A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor... |
| US-7,443,022 |
Board-on-chip packages The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A ... |
| US-7,443,009 |
N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is... |
| US-7,443,006 |
Photon amplification of image sensors A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer... |
| US-7,442,979 |
Reduced cell-to-cell shorting for memory arrays Bottom electrodes of memory cell capacitors are recessed to prevent electrical shorts between neighboring memory cells. A partially fabricated memory cell... |
| US-7,442,977 |
Gated field effect devices This invention includes gated field effect devices, and methods of forming gated field effect devices. In one implementation, a gated field effect device... |
| US-7,442,976 |
DRAM cells with vertical transistors The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain... |
| US-7,442,970 |
Active photosensitive structure with buried depletion layer An imager pixel has a photosensitive JFET structure having a channel region located above a buried charge accumulation region. The channel region has a... |
| US-7,442,910 |
High dynamic range cascaded integration pixel cell A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a... |
| US-7,442,655 |
Selective oxidation methods and transistor fabrication methods The invention includes selective oxidation methods and transistor fabrication methods. In one implementation, a selective oxidation method includes positioning a... |
| US-7,442,643 |
Methods of forming conductive elements using organometallic layers and
flowable, curable conductive materials A conductive element is formed on a substrate by forming an organometallic layer on at least a portion of a surface of the substrate, heating a portion of the... |
| US-7,442,633 |
Decoupling capacitor for high frequency noise immunity Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the... |
| US-7,442,608 |
Methods of fabricating a semiconductor device using angled implantation Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a... |
| US-7,442,600 |
Methods of forming threshold voltage implant regions The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger... |
| US-7,442,578 |
Underfill compounds including electrically charged filler elements,
microelectronic devices having underfill... Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler... |
| US-7,442,472 |
Methods of forming reticles The invention includes reticle constructions and methods of forming reticle constructions. In a particular aspect, a method of forming a reticle includes... |
| US-7,442,319 |
Poly etch without separate oxide decap The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon... |
| US-7,441,949 |
System and method for providing temperature data from a memory device
having a temperature sensor A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature... |
| US-7,441,172 |
DVI link with parallel test data An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random... |
| US-7,440,860 |
Sequential unique marking The present invention comprises a method of sequential unique marking comprising providing a multi-die handling device with a plurality of semiconductor devices... |
| US-7,440,344 |
Level shifter for low voltage operation A voltage level translator boosts the gate voltage of a transistor, and increases the gate to source voltage, to allow operation over a wider range of supply... |
| US-7,440,339 |
Stacked columnar 1T-nMTj MRAM structure and its method of formation and
operation This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading... |
| US-7,440,336 |
Memory device having terminals for transferring multiple types of data A memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary... |
| US-7,440,332 |
Low power multiple bit sense amplifier A sense amplifier for multiple level flash memory cells is comprised of a voltage ramp generator that generates a ramp voltage signal. Reference sense amplifiers... |
| US-7,440,321 |
Multiple select gate architecture with select gates of different lengths A portion of a memory array has a string of two or more non-volatile memory cells, a first select gate coupled in series with one non-volatile memory cell of the... |
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