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Patent # Description
US-7,323,767 Standoffs for centralizing internals in packaging process
A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the...
US-7,323,756 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,323,755 Method of composite gate formation
Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes...
US-7,323,739 Semiconductor device having recess and planarized layers
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a...
US-7,323,738 MIS capacitor and method of formation
An MIS capacitor with low leakage and high capacitance is disclosed. A layer of hemispherical grained polysilicon (HSG) is formed as a lower electrode. Prior to...
US-7,323,737 DRAM constructions and electronic systems
The invention includes methods in which metal oxide dielectric materials are deposited over barrier layers. The barrier layers can comprise compositions of metal...
US-7,323,424 Semiconductor constructions comprising cerium oxide and titanium oxide
The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can...
US-7,323,412 Atomic layer deposition methods, and methods of forming materials over semiconductor substrates
The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times...
US-7,323,400 Plasma processing, deposition and ALD methods
A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing...
US-7,323,380 Single transistor vertical memory gain cell
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain...
US-7,323,353 Resonator for thermo optic device
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is...
US-7,323,292 Process for using photo-definable layers in the manufacture of semiconductor devices and resulting structures...
A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of...
US-7,323,291 Dual layer workpiece masking and manufacturing process
The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described...
US-7,323,231 Apparatus and methods for plasma vapor deposition processes
One aspect of the invention is directed toward a method of forming a conductive layer on a microfeature workpiece. In one embodiment, the method comprises...
US-7,323,064 Supercritical fluid technology for cleaning processing chambers and systems
The invention includes a method of cleaning a processing chamber by introducing supercritical fluid into the processing chamber. A residue over an internal...
US-7,322,511 Apparatus and method for printing micro metal structures
A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using...
US-7,322,002 Erasure pointer error correction
Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in...
US-7,321,951 Method for testing flash memory power loss recovery
Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or...
US-7,321,504 Static random access memory cell
A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter...
US-7,321,455 Microelectronic devices and methods for packaging microelectronic devices
Microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, a method includes placing a plurality of...
US-7,321,160 Multi-part lead frame
A multi-part lead frame semiconductor device assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed...
US-7,321,150 Semiconductor device precursor structures to a double-sided capacitor or a contact
A method of forming a double-sided capacitor using at least one sacrificial structure, such as a sacrificial liner or a sacrificial plug. A sacrificial liner is...
US-7,321,149 Capacitor structures, and DRAM arrays
A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer....
US-7,321,148 Capacitor constructions and rugged silicon-containing surfaces
The invention encompasses a method of forming a rugged silicon-containing surface. A layer comprising amorphous silicon is provided within a reaction chamber at...
US-7,320,933 Double bumping of flexible substrate for first and second level interconnects
An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with...
US-7,320,911 Methods of forming pluralities of capacitors
A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes comprising sidewalls. The plurality of capacitor electrodes...
US-7,320,049 Detection circuit for mixed asynchronous and synchronous memory operation
A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit...
US-7,319,935 System and method for analyzing electrical failure data
A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having...
US-7,319,728 Delay locked loop with frequency control
A delay locked loop includes a delay line for delaying an input signal generated from an external signal. A delay controller controls the delay line to keep the...
US-7,319,629 Method of operating a dynamic random access memory cell
A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory...
US-7,319,621 Reducing DQ pin capacitance in a memory device
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance. In...
US-7,319,620 Input and output buffers having symmetrical operating characteristics and immunity from voltage variations
A pair of self-biased differential amplifiers having a non-symmetrical topology are combined to provide a self-biased differential amplifier having a symmetrical...
US-7,319,613 NROM flash memory cell with integrated DRAM
A memory device that is comprised of a dynamic random access memory (DRAM) capacitor and a nitride read only memory (NROM) transistor. The memory device provides...
US-7,319,605 Conductive structure for microelectronic devices and methods of fabricating such structures
A conductive structure for gate lines and local interconnects in microelectronic devices. The conductive structure can be used in memory cells for SRAM devices...
US-7,319,340 Integrated circuit load board and method having on-board test circuit
An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The...
US-7,319,273 Methods and apparatus for a flexible circuit interposer
A flexible circuit interposer includes a flexible circuit substrate which allows in-situ probing of an attached device during, for example, circuit debugging,...
US-7,319,218 Method and apparatus for pixel signal binning and interpolation in column circuits of a sensor circuit
A binning circuit and related method, wherein pixel signals from column circuits in a sensor circuit are sampled and interpolated. The binning circuit samples...
US-7,319,075 Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes...
A selective dry etch process includes use of an etchant that includes C.sub.2H.sub.xF.sub.y, where x is an integer from three to five, inclusive, where y is an...
US-7,319,071 Methods for forming a metallic damascene structure
In damascene process integration, a reducing plasma is applied after the etch stop or barrier layer is opened over a copper layer. Currently known methods for...
US-7,318,204 Synthesizing semiconductor process flow models
Systems and methods of modeling a best-guess semiconductor process flow for fabricating a desired semiconductor device are provided. The best-guess process flow...
US-7,318,181 ROM-based controller monitor in a memory device
A circuit to monitor the activity of a memory device during program/erase operations that are managed by a ROM-based microcontroller. Different signals can be...
US-7,318,167 DDR II write data capture calibration
A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., "1100,"...
US-7,318,146 Peripheral device with hardware linked list
A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers...
US-7,317,647 Noise suppression in memory device sensing
NAND memory devices utilize sensing devices for sensing a programmed state of a nonvolatile memory cell or writing a data value to a nonvolatile memory cell....
US-7,317,635 User configurable commands for flash memory
A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of...
US-7,317,579 Method and apparatus providing graded-index microlenses
Microlenses are fabricated with a refractive-index gradient. The refractive-index gradient is produced in a microlens material such that the refractive index is...
US-7,317,567 Method and apparatus for providing color changing thin film material
An electrochromic device and methods for forming the same are provided. The device includes first and second electrodes. A layer of ...
US-7,317,521 Particle detection method
A method for detecting on a substrate used in the fabrication of integrated devices comprises the steps of (1) contacting the substrate with a monomer, wherein...
US-7,317,480 Imaging apparatus providing black level compensation of a successive approximation A/D converter
Image sensor with a successive approximation A/D converter that automatically compensates for black level and provides a signal indicative of the difference...
US-7,317,446 Method for entering data into a computer using a peripheral input device having a retractable cord
The invention, in one embodiment, is a method for entering data into a computer. The method includes anchoring an electrical cord connecting a peripheral input...
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