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Patent # Description
US-7,346,817 Method and apparatus for generating and detecting initialization patterns for high speed DRAM systems
A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal...
US-7,346,182 Electroacoustic transducer and method for manufacturing the same
A diaphragm subassembly comprises a voice coil, a diaphragm, a frame, and a pair of terminal members. A magnetic circuit unit comprises a yoke, a magnet, and a...
US-7,346,162 Public key cryptography using matrices
The invention provides techniques for secure messages transmission using a public key system to exchange secret keys. A first entity creates public and private...
US-7,345,937 Open digit line array architecture for a memory array
A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and...
US-7,345,932 Low power dissipation voltage generator
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a...
US-7,345,924 Programming memory devices
A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether...
US-7,345,922 Position based erase verification levels in a flash memory device
The location of a cell to be erase verified is determined. The erase verification threshold voltage is then set. The threshold voltage is changed in response to...
US-7,345,918 Selective threshold voltage verification and compaction
Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of...
US-7,345,575 Radio frequency data communications device with adjustable receiver sensitivity and method
A device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving circuitry provided on the monolithic integrated...
US-7,345,515 Low power and low timing jitter phase-lock loop and method
A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase...
US-7,345,358 Copper interconnect for semiconductor device
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape...
US-7,345,350 Process and integration scheme for fabricating conductive components, through-vias and semiconductor components...
A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an...
US-7,345,333 Double sided container process used during the manufacture of a semiconductor device
A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact...
US-7,345,332 Semiconductor constructions
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and...
US-7,345,299 Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon...
The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile...
US-7,345,269 Method and apparatus providing configurable current source device for image sensors with a selective current at...
A configurable current source for imager readout system that can be operated as a simple-current-source or as a cascode-current-source. The configurable current...
US-7,344,977 Method of electroplating a substance over a semiconductor substrate
The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate...
US-7,344,975 Method to reduce charge buildup during high aspect ratio contact etch
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer...
US-7,344,969 Stacked die in die BGA package
Semiconductor devices and stacked die assemblies, and methods of fabrication are provided. In various embodiments, the die assembly comprises a first die mounted...
US-7,344,948 Methods of forming transistors
The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a...
US-7,344,946 Structure for amorphous carbon based non-volatile memory
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a...
US-7,344,942 Isolation regions for semiconductor devices and their formation
A hard mask layer is formed and patterned overlying a semiconductor substrate of a semiconductor device. The patterned hard mask layer exposes two or more areas...
US-7,344,937 Methods and apparatus with silicide on conductive structures
Exemplary embodiments of the invention provide pixel circuits having transistors with silicide on top of their gate stacks. In the exemplary embodiments,...
US-7,344,921 Integrated circuit device having reduced bow and method for making same
An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of...
US-7,344,899 Die assembly and method for forming a die on a wafer
A method for forming a die on a wafer is provided. The method includes forming on a wafer a die having an active portion that includes integrated circuitry. The...
US-7,344,755 Methods and apparatus for processing microfeature workpieces; methods for conditioning ALD reaction chambers
The present disclosure provides methods and apparatus that may be used to process microfeature workpieces, e.g., semiconductor wafers. Some aspects have...
US-7,344,061 Multi-functional solder and articles made therewith, such as microelectronic components
Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the...
US-7,343,444 Reconfigurable memory module and method
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided...
US-7,342,409 System for testing semiconductor components
A system for testing semiconductor components includes an interconnect, an alignment system for aligning a substrate to the interconnect, a bonding system for...
US-7,342,319 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
Integrated circuit packages that connect solder balls between solder ball pads of a die and substrate pads of a printed circuit board (PCB). The solder balls are...
US-7,342,273 Applying epitaxial silicon in disposable spacer flow
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a...
US-7,342,272 Flash memory with recessed floating gate
A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer...
US-7,342,212 Analog vertical sub-sampling in an active pixel sensor (APS) image sensor
An active pixel sensor (APS) image sensor comprises an array of pixel circuits corresponding to rows and columns of pixels, a plurality of amplifiers that buffer...
US-7,341,957 Masking structure having multiple layers including amorphous carbon layer
A masking structure having multiple layers is formed. The masking structure includes an amorphous carbon layer and a cap layer formed over the amorphous carbon...
US-7,341,951 Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and...
US-7,341,947 Methods of forming metal-containing films over surfaces of semiconductor substrates
The invention includes a method of forming a metal-containing film over a surface of a semiconductor substrate. The surface is exposed to a supercritical fluid....
US-7,341,931 Methods of forming low resistivity contact for an integrated circuit device
Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or...
US-7,341,909 Methods of forming semiconductor constructions
The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically...
US-7,341,906 Method of manufacturing sidewall spacers on a memory device, and device comprising same
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall...
US-7,341,901 Semiconductor processing methods of forming integrated circuitry
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a...
US-7,341,881 Methods of packaging and testing microelectronic imaging devices
Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging...
US-7,341,502 Methods and systems for planarizing workpieces, e.g., microelectronic workpieces
Planarizing workpieces, e.g., microelectronic workpieces, can employ a process indicator which is adapted to change an optical property in response to a...
US-7,340,668 Low power cost-effective ECC memory system and method
A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The...
US-7,340,584 Sequential nibble burst ordering for data
A combination of circuits for use in a memory device is comprised of a decode circuit responsive to a first portion of address information for identifying a word...
US-7,339,839 Triggering of IO equilibrating ending signal with firing of column access signal
A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ...
US-7,339,838 Method and apparatus for supplementary command bus
An electronic system according to various aspects of the present invention includes a memory having a location-specific command interface and a general command...
US-7,339,830 One transistor SOI non-volatile random access memory cell
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried...
US-7,339,818 Spintronic devices with integrated transistors
The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a...
US-7,339,812 Stacked 1T-nmemory cell structure
This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell...
US-7,339,811 Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operation
This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading...
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