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Patent # Description
US-7,294,549 Vertical floating gate transistor
A floating gate transistor has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a...
US-7,294,545 Selective polysilicon stud growth
A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by...
US-7,294,527 Method of forming a memory cell
The invention relates to the fabrication of a resistance variable material cell or programmable metallization cell. The processes described herein can form a...
US-7,294,049 Method and apparatus for removing material from microfeature workpieces
Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having...
US-7,294,040 Method and apparatus for supporting a microelectronic substrate relative to a planarization pad
A method and apparatus for planarizing a microelectronic substrate. In one embodiment, one surface of the microelectronic substrate is engaged with a planarizing...
US-7,293,526 Plasma reaction chamber liner consisting essentially of osmium
The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or...
US-7,292,497 Multi-bank memory
A multi-bank memory device includes rows and columns of memory cores. Each row includes memory cores from one bank interleaved with memory cores from another...
US-7,292,491 Method and apparatus for controlling refresh operations in a dynamic memory device
A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The...
US-7,292,489 Circuits and methods of temperature compensation for refresh oscillator
A memory device has refresh cycles to refresh memory cells of the memory device. The time interval between one refresh cycle to the next refresh cycle is a...
US-7,292,487 Independent polling for multi-page programming
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the...
US-7,292,476 Programming method for NAND EEPROM
A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by...
US-7,291,920 Semiconductor structures
In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b)...
US-7,291,917 Integrated circuitry
Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one...
US-7,291,900 Lead frame-based semiconductor device packages incorporating at least one land grid array package
A lead frame-based semiconductor device package including at least one land grid array package. At least one semiconductor die is mounted to an interposer...
US-7,291,895 Integrated circuitry
A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed...
US-7,291,880 Transistor assembly
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related...
US-7,291,822 Amplification with feedback capacitance for photodetector signals
Signals from an imager pixel photodetector are received by an amplifier having capacitive feedback, such as a capacitive transimpedance amplifier (CTIA). The...
US-7,291,563 Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer...
The invention includes methods of etching substrates, methods of forming features on substrates, and methods of depositing a layer comprising silicon, carbon and...
US-7,291,555 Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal...
A method of forming a reaction product includes providing a semiconductor substrate comprising a first material. A second material is formed over the first...
US-7,291,543 Thin flip-chip method
Methods for thinning a bumped semiconductor wafer, as well as methods for producing flip-chips of very thin profiles, are disclosed. According to the methods of...
US-7,291,519 Methods of forming transistor constructions
The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body...
US-7,291,425 Radiation patterning tools, and methods of forming radiation patterning tools
The invention includes, for example, a radiation patterning tool which can be utilized to form relatively circular contacts in situations in which an array of...
US-7,290,242 Pattern generation on a semiconductor surface
A method of forming a pattern of elements is shown. In one embodiment, the method is used to create a reticle. In another embodiment, the method is used to...
US-7,289,384 Method for writing to multiple banks of a memory device
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows...
US-7,289,378 Reconstruction of signal timing in integrated circuits
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of...
US-7,289,363 Memory cell repair using fuse programming method in a flash memory device
A method for repairing cells of a flash memory array includes using a fuse memory array circuit. The fuse memory cells are initially programmed. The locations of...
US-7,289,349 Resistance variable memory element with threshold device and method of forming the same
A memory device having a memory portion connected in series with a threshold device between. The memory portion stores at least one bit of data based on at least...
US-7,289,347 System and method for optically interconnecting memory devices
A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled...
US-7,288,954 Compliant contact pin test assembly and methods thereof
A compliant contact pin assembly and a contactor card and methods for testing therewith are provided. The compliant contact pin assembly includes a contact pin...
US-7,288,953 Method for testing using a universal wafer carrier for wafer level die burn-in
A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer...
US-7,288,819 Stable PD-SOI devices and methods
One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an...
US-7,288,817 Reverse metal process for creating a metal silicide transistor gate structure
The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal...
US-7,288,808 Capacitor constructions with enhanced surface area
A capacitor fabrication method may include forming a first capacitor electrode over a substrate, the first electrode having an inner surface area per unit area...
US-7,288,806 DRAM arrays
The invention includes memory arrays, and methods which can be utilized for forming memory arrays. A patterned etch stop can be used during memory array...
US-7,288,784 Structure for amorphous carbon based non-volatile memory
A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a...
US-7,288,757 Microelectronic imaging devices and associated methods for attaching transmissive elements
Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one...
US-7,288,441 Method for two-stage transfer molding device to encapsulate MMC module
A method for fabricating a semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor...
US-7,288,431 Molded stiffener for thin substrates
A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is...
US-7,287,327 Electret capacitor microphone and method for producing the same
A method for producing an electret capacitor microphone high in sensitivity and stable in acoustic characteristic. A PET film stretched with predetermined...
US-7,287,326 Methods of forming a contact pin assembly
A compliant contact pin assembly method for making is provided. The compliant contact pin assembly includes a contact pin formed from a portion of a substrate...
US-7,287,108 Capacitive multidrop bus compensation
The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes...
US-7,286,428 Offset compensated sensing for magnetic random access memory
An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the...
US-7,286,417 Low power dissipation voltage generator
A voltage generator circuit is described for providing a regulated voltage, such as a negative word line voltage in a semiconductor memory. The generator uses a...
US-7,286,378 Serial transistor-cell array architecture
A memory device having memory cells in which a single access transistor controls the grounding of at least four storage elements, such as resistive storage...
US-7,286,180 CMOS image sensor with a low-power architecture
A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized....
US-7,285,986 High speed, low power CMOS logic gate
A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an...
US-7,285,979 Apparatus and method for independent control of on-die termination for output buffers of a memory device
An apparatus and method providing independent control of on-die termination (ODT) of output buffers. The ODTs for the buffer circuits of an input/output (I/O)...
US-7,285,971 Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress...
A testing apparatus and method for testing integrated circuits is disclosed wherein a device under test is continuously maintained at a desired set point...
US-7,285,970 Load board socket adapter and interface method
A load board adapter which is removably attachable to a load board and provides removable and replaceable sockets for individual integrated circuit packages to...
US-7,285,850 Support elements for semiconductor devices with peripherally located bond pads
A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding...
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