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Patent # Description
US-7,307,353 Technique for attaching die to leads
A semiconductor die assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminates over...
US-7,307,348 Semiconductor components having through wire interconnects (TWI)
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact....
US-7,307,327 Reduced crosstalk CMOS image sensors
CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A...
US-7,307,306 Etch mask and method of forming a magnetic random access memory structure
A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering...
US-7,306,991 Stepped gate configuration for non-volatile memory
A memory device having a field effect transistor with a stepped gate dielectric and a method of making the same are herein disclosed. The stepped gate dielectric...
US-7,306,974 Microelectronic devices and methods for manufacturing and operating packaged microelectronic device assemblies
Packaged microelectronic devices, methods for packaging microelectronic devices, and methods of operating microelectronic devices. In one embodiment, a packaged...
US-7,306,954 Process flow for building MRAM structures
MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching...
US-7,306,506 In-situ chemical-mechanical planarization pad metrology using ultrasonic imaging
Chemical-mechanical planarization (CMP) apparatus and methods for detecting polishing pad properties using ultrasonic imaging is presented. An ultrasonic probe...
US-7,305,514 Command sequence for optimized power consumption
Power consumption by a memory device may be controlled by maintaining data input buffers in an off state until a command sequence containing a specified command...
US-7,304,638 Computer touch screen adapted to facilitate selection of features at edge of screen
In one embodiment of the invention, a hot spot is normally centered in an area of contact between a user's finger and a touch screen to position the hot spot on...
US-7,304,516 Method and apparatus for digital phase generation for high frequency clock applications
An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal....
US-7,304,491 Interconnect for testing semiconductor components
An interconnect for testing semiconductor components includes interconnect contacts configured for bonding to, and then separation from component contacts on the...
US-7,304,380 Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
US-7,304,375 Castellation wafer level packaging of integrated circuit chips
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled...
US-7,304,368 Chalcogenide-based electrokinetic memory element and method of forming the same
Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a...
US-7,304,353 Formation of standard voltage threshold and low voltage threshold MOSFET devices
Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first...
US-7,303,991 Atomic layer deposition methods
The invention includes an atomic layer deposition method of forming a layer of a deposited composition on a substrate. The method includes positioning a...
US-7,303,939 Electro- and electroless plating of metal in the manufacture of PCRAM devices
Non-volatile, resistance variable memory devices, integrated circuit elements, and methods of forming such devices are provided. According to one embodiment of a...
US-7,303,938 Gated isolation structure for imagers
Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field...
US-7,303,931 Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces
Microfeature workpieces having microlenses and methods of forming microlenses on microfeature workpieces are disclosed herein. In one embodiment, a method for...
US-7,303,637 Method of cleaning semiconductor surfaces
Devices and methods of cleaning are described. The methods, and devices formed by the methods have a number of advantages. Embodiments are shown that include...
US-7,303,471 Method and system for transferring data to an electronic toy or other electronic device
A method for transferring data from a display device to an electronic device includes displaying a visual pattern on the display device. The visual pattern...
US-7,303,404 Contact and electrical connecting apparatus
A contact includes: a first and a second conductive contact pieces and at least one sheet-like electrical insulator such as polyimide. Each contact piece has a...
US-7,302,519 Distributed content addressable memory
The present invention provides a large capacity distributed content addressable memory (CAM) made up of a plurality of smaller CAMs interconnected on a high...
US-7,302,111 Graphics engine for high precision lithography
The present invention includes a method to use a phase modulating micromirror array to create an intensity image that has high image fidelity, good stability...
US-7,301,221 Controlling diffusion in doped semiconductor regions
A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of...
US-7,301,190 Structures and methods to enhance copper metallization
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a...
US-7,300,873 Systems and methods for forming metal-containing layers using vapor deposition processes
A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use...
US-7,300,870 Systems and methods of forming refractory metal nitride layers using organic amines
A method of forming (and apparatus for forming) refractory metal nitride layers (including silicon nitride layers), such as a tantalum nitride barrier layer, on...
US-7,300,857 Through-wafer interconnects for photoimager and memory wafers
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making...
US-7,300,839 Selective polysilicon stud growth
A memory cell having a bit line contact is provided. The memory cell may be a 6F.sup.2 memory cell. The bit line contact may have a contact hole bounded by...
US-7,300,821 Integrated circuit cooling and insulating device and method
A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge...
US-7,300,526 Method and system for removal of contaminates from phaseshift photomasks
A system and method to clean the pellicle frame and adhesive ring of a photomask reticle are described. One embodiment includes a cover that isolates the...
US-7,299,381 Discrete tests for weak bits
A testing method for semiconductor memory that selects memory cells adjacent to the periphery of the memory array and to a memory twist. These memory cells are...
US-7,299,329 Dual edge command in DRAM
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-7,298,638 Operating an electronic device having a vertical gain cell that includes vertical MOS transistors
A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating...
US-7,298,453 Method and apparatus for irradiating a microlithographic substrate
A method and apparatus for exposing a radiation-sensitive material of a microlithographic substrate to a selected radiation. The method can include directing the...
US-7,298,425 Method for assisting video compression in a computer system
One embodiment of the present invention provides a method that facilitates compression of video data in a computer system by performing the time-consuming task...
US-7,298,406 Ground referenced pixel reset
A ground referenced pixel reset circuit is disclosed. The ground referenced pixel reset circuit supplies a pixel with a reset signal such that when the reset...
US-7,298,401 Method and apparatus for removing flicker from images
Method and apparatus for removing image artifacts from an image of a scene illuminated by a periodically varying light source such as a fluorescent light source....
US-7,298,031 Multiple substrate microelectronic devices and methods of manufacture
A microelectronic device and method for manufacture. In one embodiment, two microelectronic substrates are directly bonded to each other without an intermediate...
US-7,298,025 Microelectronic component assemblies and microelectronic component lead frame structures
The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead...
US-7,298,024 Transparent amorphous carbon structure in semiconductor devices
A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is...
US-7,298,000 Conductive container structures having a dielectric cap
Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive...
US-7,297,995 Transparent metal shielded isolation for image sensors
An isolation region formed in a substrate and lined with a transparent metal layer. The isolation region provides isolation between adjacent active areas of an...
US-7,297,917 Readout technique for increasing or maintaining dynamic range in image sensors
The apparatus and method provide a readout technique and circuit for increasing or maintaining dynamic range of an image sensor. The readout technique and...
US-7,297,915 Compensation methods and systems for imaging detectors
Imaging arrays typically include thousands or millions of photodetectors that convert sensed light into corresponding electric signals, which are ultimately...
US-7,297,639 Methods for etching doped oxides in the manufacture of microfeature devices
Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching...
US-7,297,637 Use of pulsed grounding source in a plasma reactor
A method for grounding a semiconductor substrate pedestal during a portion of a high voltage power bias oscillation cycle to reduce or eliminate the detrimental...
US-7,297,623 Etch stop layer in poly-metal structures
In accordance with one embodiment of the present invention, a method of interfacing a poly-metal structure and a semiconductor substrate is provided where an...
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