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Patent # Description
US-9,336,410 Nonvolatile memory internal signature generation
A nonvolatile memory device generates a signature using a private key and contents within the memory device. The signature is stored in a secure area within the...
US-9,336,086 Apparatuses and methods including error correction code organization
Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory...
US-9,336,084 Error detection for multi-bit memory
Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of...
US-9,336,083 Apparatus and methods of programming memory cells using adjustable charge state level(s)
Apparatus and methods are disclosed, including a method of programming involving determining an error rate for the memory cells, and programming the memory...
US-9,336,082 Validating persistent memory content for processor main memory
Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.
US-9,335,372 Apparatus and methods for delay line testing
This disclosure relates to delay line test circuits and methods. In one aspect, an integrated circuit (IC) can include a plurality of delay lines, a selection...
US-D755,657 Mobile electronic emergency responder
US-9,331,989 Secure shared key sharing systems and methods
Systems and methods used to securely communicate a shared key to devices. One embodiment describes a method to securely communicate a shared key to a first...
US-9,331,702 Apparatuses and methods for compensating for power supply sensitivities of a circuit in a clock path
Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing...
US-9,331,699 Level shifters, memory systems, and level shifting methods
Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive...
US-9,331,646 Input buffer apparatuses and methods
Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a...
US-9,331,275 Switching device structures and methods
Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a...
US-9,331,269 Spin transfer torque memory cells
Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an...
US-9,331,252 Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting...
Wavelength converters, including polarization-enhanced carrier capture converters, for solid state lighting devices, and associated systems and methods are...
US-9,331,236 Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems...
Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several...
US-9,331,203 Devices with cavity-defined gates and methods of making the same
Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent...
US-9,331,083 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus...
US-9,330,975 Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias
A method of forming a through-substrate via includes forming a through-substrate via opening at least partially through a substrate from one of opposing sides...
US-9,330,934 Methods of forming patterns on substrates
Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the...
US-9,330,932 Methods of fabricating features associated with semiconductor substrates
Some embodiments include a method in which a mixture of polynucleotide structures comprises a set of surface shapes. Surface shapes of some polynucleotide...
US-9,330,914 Methods of forming line patterns in substrates
A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide...
US-9,330,794 DRAM-based anti-fuse cells
Apparatuses and methods for programming and reading from anti-fuse cells are disclosed herein. For example, a semiconductor device may include a plurality of...
US-9,330,789 Short-checking methods
In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing...
US-9,330,777 Memory program disturb reduction
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first...
US-9,330,756 Apparatuses and methods for sensing using an integration component
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a...
US-9,329,990 Host controlled enablement of automatic background operations in a memory device
A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host...
US-9,329,623 Apparatuses, integrated circuits, and methods for synchronizing data signals with a command signal
Apparatuses, integrated circuits, and methods are disclosed for synchronizing data signals with a command signal. In one such example apparatus, an input...
US-9,329,336 Method of forming a hermetically sealed fiber to chip connection
Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated...
US-9,329,206 Probe card and method for manufacturing the same
A method for manufacturing a probe card is provided wherein probes are held in a holding plate such that the respective probes correspond to through holes with...
US-9,326,338 Multi-junction solid state transducer devices for direct AC power and associated systems and methods
Multi-junction solid-state transducer (SST) devices and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system...
US-9,325,330 Semiconductor device including a clock adjustment circuit
Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in...
US-9,324,945 Memory cells and methods of forming memory cells
A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable...
US-9,324,943 Filamentary memory devices and methods
Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices...
US-9,324,905 Solid state optoelectronic device with preformed metal support substrate
A wafer-level process for manufacturing solid state lighting ("SSL") devices using large-diameter preformed metal substrates is disclosed. A light emitting...
US-9,324,690 Signal delivery in stacked device
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
US-9,324,676 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of...
US-9,324,611 Corrosion resistant via connections in semiconductor substrates and methods of making same
Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present...
US-9,324,434 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-9,324,423 Apparatuses and methods for bi-directional access of cross-point arrays
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of...
US-9,324,410 Semiconductor memory device having an output buffer controller
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the...
US-9,324,398 Apparatuses and methods for targeted refreshing of memory
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines...
US-9,324,391 Dual event command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,323,994 Multi-level hierarchical routing matrices for pattern-recognition processors
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or...
US-9,323,608 Integrity of a data bus
A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An...
US-9,319,349 Encapsulation enabled PCIE virtualisation
There is herein described a method for transmitting data packets from a first device through a switch to a second device. The method is performed at an...
US-9,318,699 Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first...
US-9,318,493 Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-9,318,438 Semiconductor structures comprising at least one through-substrate via filled with conductive materials
A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The...
US-9,318,430 Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components,...
A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion...
US-9,318,416 Semiconductor device including conductive layer with conductive plug
Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected...
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