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Patent # Description
US-9,842,976 Vertical light emitting devices with nickel silicide bonding and methods of manufacturing
Various embodiments of light emitting devices, assemblies, and methods of manufacturing are described herein. In one embodiment, a method for manufacturing a...
US-9,842,965 Textured devices
Epitaxial growth methods and devices are described that include a textured surface on a substrate in a liquid crystal device. Geometry of the textured surface...
US-9,842,847 Drain select gate formation methods and apparatus
Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate...
US-9,842,840 Transistors and memory arrays
Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post...
US-9,842,839 Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array...
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material....
US-9,842,661 Ferroelectric memory cell recovery
Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell...
US-9,842,652 Memory array with power-efficient read architecture
Various embodiments comprise apparatuses and methods including a three-dimensional memory apparatus having upper strings and lower strings. The upper strings...
US-9,842,649 Resistance variable element methods and apparatuses
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
US-9,842,633 Tracking and correction of timing signals
Various embodiments include apparatus and methods to track and/or correct timing signals. Timing signals generated from an interface can be compared to the...
US-9,842,058 Locking entries into translation lookaside buffers
Two translation lookaside buffers may be provided for simpler operation in some embodiments. A hardware managed lookaside buffer may handle traditional...
US-9,838,624 Anti-eclipse circuitry with tracking of floating diffusion reset level
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to...
US-9,837,383 Interconnect structure with improved conductive properties and associated systems and methods
Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive...
US-9,831,428 Memory cell with independently-sized electrode
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle...
US-9,831,287 Memory devices and memory device forming methods
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive...
US-9,831,246 JFET device structures and methods for fabricating the same
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a...
US-9,831,002 Apparatuses and methods for operating a memory device
Subject matter described pertains to apparatuses and methods for operating a memory device.
US-9,830,999 Comparison operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a...
US-9,830,970 Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming...
Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and...
US-9,830,955 Data shifting
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
US-9,830,267 Continuous page read for memory
Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
US-9,830,087 Memory wear leveling
Systems and methods for intra-sector re-ordered wear leveling include: detecting, in a memory device, a high wear sub-sector having a high wear level, the...
US-9,824,770 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-9,824,725 Semiconductor device with single ended main I/O line
Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data...
US-9,824,010 Multiple data channel memory module architecture
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a...
US-9,824,004 Methods and apparatuses for requesting ready status information from a memory
Methods and apparatuses are disclosed for requesting ready status information from a memory. One example apparatus includes a memory and a host coupled to the...
US-9,823,864 Systems and methods for throttling packet transmission in a scalable memory system protocol
A method may include transmitting, via a processor, a plurality of packets to a receiving component, such that the plurality of packets corresponds to a...
US-9,818,756 Methods of forming a charge-retaining transistor having selectively-formed islands of charge-trapping material...
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes...
US-9,818,728 Interconnect structure with redundant electrical connectors and associated systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,625 Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,818,622 Uniform back side exposure of through-silicon vias
Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate...
US-9,818,462 Apparatuses and methods for providing internal clock signals of different clock frequencies in a memory device
Apparatuses and methods for providing internal clock signals of different clock frequencies in a semiconductor device are described in the present application....
US-9,818,459 Invert operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,817,678 Methods and systems for detection in a state machine
A device including a data analysis element including a plurality of memory cells. The memory cells analyze at least a portion of a data stream and output a...
US-9,817,392 Photolithography systems and associated methods of overlay error correction
Several embodiments of photolithography systems and associated methods of overlay error correction are disclosed herein. In one embodiment, a method for...
US-9,813,067 Clock signal and supply voltage variation tracking
Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a...
US-9,812,606 Solid-state transducer devices with optically-transmissive carrier substrates and related systems, methods, and...
Semiconductor device assemblies having solid-state transducer (SST) devices and associated semiconductor devices, systems, and are disclosed herein. In one...
US-9,812,455 Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias
A method of forming conductive vias comprises forming at least three parallel line constructions elevationally over a substrate. The line constructions...
US-9,812,415 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
US-9,811,651 System and method for controlling user access to an electronic device
A method and system for authenticating a user to access a computer system. The method comprises communicating security information to the computer system, and...
US-9,811,258 Methods for controlling host memory access with memory devices and systems
The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment...
US-9,806,129 Cross-point memory and methods for fabrication of same
The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same....
US-9,805,828 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-9,805,817 Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US-9,805,801 Memory devices and methods of their operation during a programming operation
Methods of operating a memory device during a programming operation, and memory devices so configured, including increasing a voltage applied to a selected...
US-9,805,792 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-9,805,789 Oxide based memory
Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory...
US-9,805,786 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-9,805,783 Semiconductor device
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a...
US-9,805,772 Apparatuses and methods to selectively perform logical operations
The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry...
US-9,804,350 Method of forming a hermetically sealed fiber to chip connections
Disclosed are methods of providing a hermetically sealed optical connection between an optical fiber and an optical element of a chip and a photonic-integrated...
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