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Patent # Description
US-9,356,157 Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices
Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an...
US-9,356,155 Semiconductor device structures and arrays of vertical transistor devices
A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region...
US-9,356,145 Electronic device with asymmetric gate strain
The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced...
US-9,356,112 Charge trapping dielectric structures
A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator...
US-9,356,096 Method providing an epitaxial growth having a reduction in defects and resulting structure
Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size...
US-9,356,095 Vertical devices and methods of forming
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor...
US-9,356,028 Disposable pillars for contact formation
Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various...
US-9,356,009 Interconnect structure with redundant electrical connectors and associated systems and methods
Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die...
US-9,355,994 Build-up package for integrated circuit devices, and methods of making same
A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a...
US-9,355,992 Land grid array semiconductor device packages
A semiconductor device package includes a land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the...
US-9,355,934 Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to...
US-9,355,923 Semiconductor device with an overlay mark including segment regions surrounded by a pool region
Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a...
US-9,355,897 Methods of forming semiconductor structures
Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such...
US-9,355,837 Methods of forming and using materials containing silicon and nitrogen
Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer...
US-9,355,730 Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G...
US-9,355,718 Metallization scheme for integrated circuit
For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level...
US-9,355,709 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-9,355,026 Searching using multilevel cells and programming multilevel cells for searching
Methods of searching and methods of programming a memory are provided. In one such method of searching, a determination is made as to whether an attribute of a...
US-9,350,351 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-9,349,949 Horizontally oriented and vertically stacked memory cells
Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first...
US-9,349,945 Memory cells, semiconductor devices, and methods of fabrication
A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic...
US-9,349,803 Semiconductor graphene structures, semiconductor devices including such structures, and related methods
A semiconducting graphene structure may include a graphene material and a graphene-lattice matching material over at least a portion of the graphene material,...
US-9,349,737 Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
US-9,349,670 Semiconductor die assemblies with heat sink and associated systems and methods
Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a...
US-9,349,632 Isolation trench fill using oxide liner and nitride etch back technique with dual trench depth capability
An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such...
US-9,349,491 Repair of memory devices using volatile and non-volatile memory
Apparatus and methods for hybrid post package repair are disclosed. One such apparatus may include a package including memory cells and volatile memory. The...
US-9,349,474 Apparatuses and methods for limiting string current in a memory
Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string...
US-9,349,470 Memory read apparatus and methods
Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential,...
US-9,349,461 Applying substantially the same voltage differences across memory cells at different locations along an access...
An embodiment of a method of programming might include applying a first voltage difference across a first memory cell to be programmed, where applying the first...
US-9,349,459 Programming memory cells using smaller step voltages for higher program levels
Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first...
US-9,349,450 Memory devices and memory operational methods including single erase operation of conductive bridge memory cells
Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with...
US-9,349,445 Select devices for memory cell applications
Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more non-ohmic select devices can...
US-9,349,441 Fractional bits in memory cells
Methods, devices, modules, and systems for programming memory cells are disclosed. One method embodiment includes storing charges corresponding to a data state...
US-9,349,423 Single node power management for multiple memory devices
Some embodiments include apparatuses and methods having a node to couple to a plurality of memory devices, memory cells, and a module to perform an operation on...
US-9,349,420 Apparatuses and methods for comparing a current representative of a number of failing memory cells
Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current...
US-9,348,785 Flexible and expandable memory architectures
Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a...
US-9,348,784 Systems and methods for managing endian mode of a device
Systems, methods, and devices for managing endian-ness are disclosed. In one embodiment, a device is configured to selectively operate in one of a big-endian...
US-9,345,135 Electronic devices including two or more substrates electrically connected together and methods of forming such...
Electronic devices may include a first substrate including circuitry components within the substrate, a microscale bond pad on a surface of the substrate, and a...
US-9,344,345 Memory cells having a self-aligning polarizer
Spin torque transfer memory cells and methods of forming the same are described herein. As an example, spin torque transfer memory cells may include a...
US-9,343,677 GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
US-9,343,676 Heating phase change material
A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another...
US-9,343,674 Cross-point memory utilizing Ru/Si diode
Memory devices utilizing memory cells including a resistive element and a diode coupled in series between two conductors. The diodes include a ruthenium...
US-9,343,671 Memory cells having heaters with angled sidewalls
Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive...
US-9,343,670 Memory arrays and methods of forming same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having...
US-9,343,669 Semiconductor structures and devices including conductive lines and peripheral conductive pads
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
US-9,343,665 Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal...
US-9,343,506 Memory arrays with polygonal memory cells having specific sidewall orientations
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines...
US-9,343,479 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-9,343,462 Thyristor-based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
US-9,343,368 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
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